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參數(shù)資料
| 型號(hào)： | TDA8757CHV/17 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-612-1, HLQFP-144 |
| 文件頁數(shù)： | 8/38頁 |
| 文件大?。?/td> | 894K |
| 代理商： | TDA8757CHV/17 |
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Philips Semiconductors
TDA8757C
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 14 August 2002
16 of 38
9397 750 10111
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
where:
DRPLL = the divider ratio, which is the ratio between the pixel frequency and the
horizontal line frequency of the incoming signal. The setting of this parameter is
performed through the serial interface with bits Di0 to Di11. These bits are present
in the VCO-, divider- and phase registers.
fref = the frequency of the signal.
K0 = the VCO gain, which depends on the pixel frequency ranges given in
In the event that several combinations of R and Icp give the same result, a calculating
of the damping factor (
ξ) for each couple becomes necessary.
The combination of R and Icp whose damping factor is the closest to 1.5, generates
the optimum PLL performance.
(2)
where CZ and CP are the external capacitors of the PLL loop lter. The recommended
values are: CZ = 68 nF and CP = 150 pF.
Pin COAST is used to disconnect the PLL phase frequency detector during the frame
yback (vertical blanking) or the unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.
The COAST signal may be active either HIGH or LOW by setting bit ‘Vlevel’ in the
control register, through the serial interface (Vlevel = 0 when HIGH).
It is possible to control the phase of the ADC clock (CKADC), through the serial
interface, with the included digital phase-shift controller. The phase register (5 bits)
enables to shift the phase by steps of 11.25 deg.
The CKREF signal is resynchronized by the synchro-block on the CKADC clock. The
new reference is available on pin CKREFO. This synchronization may be done either
with the CKREF signal directly, or with the output of the divider in the PLL (see
The selection is done via the serial interface by setting bit ‘Ckrs’ in the phase register
(Ckrs = 1 when the CKREF signal is used). The polarity of the signal on pin CKREFO
is controlled through the serial interface by setting bit ‘Ckrp’ in register DEMUX
(positive polarity if Ckrp = 0). The width of this signal is xed to 8 clock cycles.
The PLL also provides a CKDATA clock. This clock is synchronized on the data
outputs regardless of the mode.
It is possible to delay the CKDATA clock with a constant time (
τ=3 ns, compared to
the outputs) by setting bit ‘Ckdd’ to logic 1 in register DEMUX. Moreover, it is possible
to invert the CKDATA clock, referenced to the outputs, by setting bit ‘Ckdp’ in
register DEMUX.
The maximum capacitive load for each clock output is 10 pF.
ξ
RC
Z
2
---------------
K
0
I
cp
DR
PLL
C
Z
C
P
+
()
-----------------------------------------------
=
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參數(shù)描述 |
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| TDA8757HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
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| TDA8759HV/8/C1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 3X8-BITS VIDEO ADC 110MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TDA8759HV/8/C1,551 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 3X8-BITS VIDEO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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