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參數(shù)資料
| 型號： | TDA758013TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 616K |
| 代理商： | TDA758013TR |
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Obsolete
Product(s)
- Obsolete
Product(s)
TDA7580
Functional description
8.2
DSP peripherals
●
Clock generation unit (CGU)
●
Stereo decoder (HWSTER)
●
Serial audio interface (SAI)
●
Tuner AGC keying DAC (KEYDAC)
●
Programmable I/O interface (I2C/BSPI)
●
Asynchronous sample rate converter (ASRC)
●
IF band pass sigma delta modulator (IFADC)
●
Digital down converter (DDC)
●
Discriminator (CORDIC)
●
RDS
●
Tuner diversity HS3I
The peripherals are mapped in the X memory space.
Most of them can be handled by interrupt, with software programmable priority.
Peripherals running at very high rate have direct access to X and Y data bus for very fast
movement from or to the core, by mean of single cycle instruction.
8.3
Clock generation unit (CGU) and oscillator
This unit is responsible for supplying all necessary clocks and synchronization signals to the
whole chip.
The control status register of this unit contains information about the current working mode
(oscillator [master mode] or clock buffer [slave mode]), the tuner clock frequency setting, the
general setup of the oscillator. This last function is performed inside the CGU, that
establishes using a self trimming algorithm, which is the current values that can bias the
oscillator: this feature lets the oscillator be independent from process parameters variation.
The values of bias current are stored in the control status register of the CGU: 4 bits for the
coarse current steps and 6 bits for the fine current steps.
In slave mode the oscillator behaves as a buffer: the chip can be then driven using an
external clock. The clock divider, placed in this unit, generates the tuner the reference clock
and can be programmed for frequencies down to 9KHz with selectable duty cycle and from
4.4Hz to 9KHz with duty cycle 50%.
An external clock can drive the XTI pin (please see
Table 12 for reference).
8.4
Stereo decoder (HWSTER)
The fully digital hardware stereo decoder does all the signal processing necessary to
demodulate an FM MPX signal which is prepared by the channel equalization algorithm in
the digital IF sampling device, providing pilot tone dependent mono/stereo switching, as well
as stereo-blend and highcut functionality.
Selectable de-emphasis time constant allow the use of this module for different FM radio
receiver standards.
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