參數(shù)資料
型號: TDA7503
廠商: STMICROELECTRONICS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁數(shù): 18/30頁
文件大?。?/td> 297K
代理商: TDA7503
25/30
TDA7503
The features of the EMI are listed below.
– Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM.
– Data word length choices of 16 or 24 bits.
– Nine DRAM address lines means 256KByte addressable DRAM.
– Refresh rate for DRAM can be chosen among eight divider factor.
– SRAM relative addressing mode with multiplexed address/data lines 16KByte addressable SRAM.
– Four SRAM Timing choices.
– Two Read Offset Registers.
Debug Interface
The Debug Port is multiplexed to both of the DSP Cores via a select pin. Only one DSP can be debugged at a
time. The debug logic is contained in the core design of the DSP. The features of the Debug Port are listed be-
low:
– Breakpoint Logic
– Trace Logic
– Single stepping
– Instruction Injection
– Program Disassembly
CORDIC Co-Processor
The CORDIC Co-Processor is used to convert rectangular to polar coordinates. .
The CORDIC Unit has an 18 Bit data path throughout. When reading 24 bit words from the DSP the upper 6
bits are truncated. When writing to the DSP the upper 6 bits are zeroed.
Either DSP may write an X and Y coordinate to the CORDIC unit and, 17 clock cycles later, the magnitude and
angle information will be available from the CORDIC Unit.
MX51 Embedded Microcontroller
The microcontroller serves as the on-chip system controller and operates from 64K of external EPROM with 1K
of internal RAM. In addition, it contains a small program in internal RAM that allows the micro to program the
external EPROM. The micro will boot a network interface program from external EPROM. If a command to pro-
gram the EPROM is received from the network then the following sequence will be initiated: The micro will read
a ROM image from the network via a network chip attached to the micro's SPI. Then the micro will switch to
running out of internal RAM and begin programming the external EPROM with the image read from the network.
This allows the personality of the system to be set after the system has been manufactured. The external
EPROM also holds the DSP programs and initializing values. The micro will copy these images to the DSP via
an on-chip host interface (HI).
In addition to the MX51 Core the following memory and control functions are required:
– Internal Memory Interface to 512 Bytes of Single Port Static RAM and 1536 Bytes of AUX-RAM
– External Memory Interface to EPROM and Memory Mapped Peripheral I/O
– Host Interface for Micro to DSP Communication
– Serial Peripheral Interface (SPI)
– Control Interface for Interrupts and GPIO
– PLL Clock Oscillator
Internal Memory Interface
The MX51 requires an internal memory interface to connect to the internal 512 RAM locations and the 1536
Auxiliary RAM.
相關(guān)PDF資料
PDF描述
TDA7511 AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP64
TDA7512 AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP64
TDA7513T AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP80
TDA7521 SPECIALTY ANALOG CIRCUIT, PQFP44
TDA7528 SPECIALTY CONSUMER CIRCUIT, PQFP64
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