參數(shù)資料
型號(hào): TDA7502E013TR
廠商: STMICROELECTRONICS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-44
文件頁數(shù): 11/26頁
文件大?。?/td> 345K
代理商: TDA7502E013TR
TDA7502
Functional description
Essentially this consists of a routine that is called when the DSP comes out of reset. There
are four different boot modes supported by the boot ROM. The first mode loads the
application program via SPI interface where Casper’s SPI is in master mode. The second
boot mode enables the debug port and waits. The third and fourth modes load the
application program via the I2C interface, one with Casper’s I2C Interface configured in slave
mode and the other in master mode. Which boot mode to enter is configured by sampling
the states of the GPIO4 and GPIO3 pins at reset as shown in the table below.
6.3.5
Serial audio interface (SAI)
The SAI is used to deliver digital audio to the DSPs from an external source. Once
processed by the DSPs, it can be returned through this interface. The features of the SAI
are listed below.
Three synchronized stereo data transmission lines
Three synchronized stereo data reception lines
Master/Slave operating modes
Transmit and receive interrupt logic triggers on left/right data pairs
Receive and transmit data registers have two locations to hold left and right data.
6.3.6
Serial peripheral interface
A serial interface allows to receive commands and data over the LAN. During an SPI
transfer, data is transmitted and received simultaneously. Both master and slave modes are
supported.
In master mode the SPI supports combination of CPOL =0/1 and CPHA =0 only, while in
slave mode all the 4 possible combinations of CPOL and CPHA are supported. See Figure
A serial clock line synchronizes shifting and sampling of the information on the two serial
data lines. A slave select line allows individual selection of a slave SPI device.
When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit
character is simultaneously shifted in a second data pin.The central element in the SPI
system is the shift register and the read data buffer. The system is single buffered in the
transfer direction and double buffered in the receive direction.
6.3.7
I2C interface
The inter integrated circuit bus is a single bidirectional two-wire bus used for efficient inter IC
control. All I2C bus compatible devices incorporate an on-chip interface which allows them
communicate directly with each other via the I2C bus.
Table 15.
Casper IC boot modes
Modes
Description
GPIO3
GPIO4
0-SPI Master
load PRAM, XRAM and YRAM from SPI
0
1-Debug
enable Debug Port
0
1
2-I2C Master
load PRAM, XRAM and YRAM from I2C1
0
3-I2C Slave
oad PRAM, XRAM and YRAM from I2C1
1
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