參數(shù)資料
型號(hào): TDA7500
廠商: STMICROELECTRONICS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 21/40頁(yè)
文件大小: 391K
代理商: TDA7500
TDA7500
28/40
I2C TIMING
Figure 16. Definition of Timing for the I2C BUS.
SPDIF TIMING
Symbol
Parameter
Test Condition
Standard Mode
I2C BUS
Fast Mode
I2C BUS
Unit
Min.
Max.
Min.
Max.
FSCL
SCLl clock frequency
0
100
0
400
kHz
tBUF
Bus free between a STOP and
Start Condition
4.7
1.3
s
tHD:STA
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated
4.0
0.6
s
tLOW
LOW period of the SCL clock
4.7
1.3
s
tHIGH
HIGH period of the SCL clock
4.0
0.6
s
tSU:STA
Set-up time for a repeated start
condition
4.7
0.6
s
tHD:DAT
DATA hold time
0
0
0.9
s
tR
Rise time of both SDA and SCL
signals
Cb in pF
1000
20+
0.1Cb
300
ns
tF
Fall time of both SDA and SCL
signals
Cb in pF
300
20+
0.1Cb
300
ns
tSU;STO
Set-up time for STOP condition
4
0.6
s
tSU:DAT
Data set-up time
250
--
100
ns
Cb
Capacitive load for each bus line
400
400
pF
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SPVL
AC input level
0.2
0.5
3.3
Vpp
SPIR
Input impedance
@ 1 kHz
–6–
k
SPHYS
Hysteresis of input
40
mV
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