參數(shù)資料
型號: TDA7445D
廠商: STMICROELECTRONICS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝: SO-28
文件頁數(shù): 13/14頁
文件大小: 194K
代理商: TDA7445D
I
2C Protocol
One data bit is transferred during each clock
pulse and the data must be stable on the high
level of the clock.
A data stream begins with a start transition and
ends with a stop transition, the data and address
words are 8 bit long.
An Acknowledge is given by the chip after each
byte transaction. The master give a SCL clock cy-
cle and the slave pull down the SDA line.
After a read, the slave does not acknowledge, i.e.
the master give a SCL clock cycle but the slave
let the pull-up value on the SDA line.
The maximum clock frequency is 100KHz when
writing and 47 Khz when reading.
The hardware address is 0x3C for write and 0x3D
for read.
WRITE SEQUENCE
START
0x3C
A
ADDR
A
DATA
A
STOP
READ SEQUENCE
Set Read Address
START
0x3C
A
ADDR
A
STOP
Read The Data
START
0x3D
A
DATA
1
STOP
Command Registers
There are 24 address accessible by I2C for all
the chip control. The parameters are either initiali-
sation states (sample frequency, data interface
modes) or effect control (volume, equalizer, Pro
Logic modes). All the registers can either be writ-
ten or read.
Register Name
Address
Data
Default
AUDIO_FREQ
0h00
Parameters
0h00
AUDIO_MODE
0h01
Parameters
0h00
SOURCE
0h02
Parameters
0h00
PROCESS
0h03
Parameters
0h00
VOLUME_L
0h04
Value
0h50
VOLUME_R
0h05
Value
0h50
VOLUME_C
0h06
Value
0h50
VOLUME_S
0h07
Value
0h50
LOUDNESS
0h08
ON/OFF
0h00
MODE
0h0F
Parameters
0h00
AUTOBALANCE
0h10
ON/OFF
0h00
WIDE_SUR-
ROUND
0h11
ON/OFF
0h00
PINK_NOISE
0h12
ON/OFF
0h00
DELAY
0h13
Value in ms
0h14
The AUDIO_FREQ register set the sample fre-
quency of data interface, this frequency have
to be set either in master or slave mode. To
avoid audible pop noise in the outputs, the
sample frequency must be changed with the
analog output unloaded.
The bit 3 bypass the ADC output to the DAc in-
put. The bit 5 selects the digital output: R/L
when 0, C/S when 1.
The AUDIO_MODE register sets the type of
data interface protocol. The bit 6 enables/dis-
ables the digital pins when in master mode
(LR, SCLK, MCLK and SDOUT).
76543210
0
0 SDOUT1
1 SDOUT2
0
00 fs=48KHz
01 fs=44.1KHz
1x fs=32KHz
0
1 HARDWARE BYPASS
AUDIO FREQ REGISTER
D98AU895B
76543210
0
0 DIGITAL ON
1 DIGITAL OFF
protocol
AUDIO MODE REGISTER
D98AU896A
TDA7445 - TDA7445D
8/14
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