參數(shù)資料
型號： TDA5345HT
廠商： NXP SEMICONDUCTORS
元件分類： 運動控制電子
英文描述： 5 V spindle & VCM driver combo
中文描述： DISK DRIVE MOTOR CONTROLLER, 2 A, PQFP64
封裝： LOW PROFILE, PLASTIC, TQFP-64
文件頁數(shù)： 11/44頁
文件大?。?/td> 213K
代理商： TDA5345HT
1999 June 10
11
Philips Semiconductors
Preliminary specification
5 V spindle & VCM driver combo
TDA5345HT
Table 2
Serial Interface REGISTERS floorplan
Note:
1.
2.
[1]
(or
[0]
) means that the bit is set to 1 (or 0) when PorN is low => default value at power up.
Use register 7 (Dac12a) for low VCM loop gain and register 8 (Dac12b) for high gain.
Control bits:
R
EGISTER
#0:
Bits [11, 9] (RegNegClk[2, 0]):
The Negative supply (-3V) regulator needs a 500 kHz clock. A programmable divider
genreates this frequency from the external clock ([15-33] Mhz). Programmation is on 3 bits.
Bits [8, 7] (PrescFactor[1, 0]):
used to select the prescaler division factor (see next section: “commutation control”).
Bit 6 (BiasCT):
used to bias the spindle centre tap at Vdd5/2 when the spindle outputs are disabled (Run/Stop = 0). The
back-EMF comparator remains operational when BiasCT = 1, to check if the spindle is running for instance.
Bit 5 (Run/Stop):
after the power supply is turned on and PorN is high, the motor will start spinning when Run/Stop is
set to ‘1’. The spindle power output starts from state code 0 (see table 3). The motor will stop when this bit is set to ‘0’.
The 3 spindle power outputs are then switched off. No brake is applied.
bit 4 (PllEnable):
enables the PLL to improve the speed accuracy.
Bit 3 (Manual):
selects the manual commutation mode (Run/Stop bit also needs to be high). When getting out of the
manual mode (=> Manual = ‘0’) and keeping the Run/Stop bit high, the internal commutation block will start from the last
state programmed in manual mode.
Bits [2, 0] (ManCom[2, 0]):
control the commutation in manual mode when Run/Stop = 1 & Manual = 1.
BIT\
REG
11
10
9
8
7
6
5
4
3
2
1
0
0
RegNeg
Clk2
[0]
StartUp
Delay3
Blank
Delay3
RegNeg
Clk1
[1]
StartUp
Delay2
Blank
Delay2
RegNeg
Clk0
[0]
StartUp
Delay1
Blank
Delay1
Presc
Factor1
[0]
StartUp
Delay0
Blank
Delay0
Presc
Factor0
[0]
ComDe
Lim3
DigOut
Mux
[1]
T_Slow
Ret4
Vcm
Retract
[0]
PllCur
0
BiasCT
[0]
Run/
Stop
[0]
ComDe
Lim1
BdGap
Adj1
[0]
T_Slow
Ret2
Dac12
Sleep
[1]
Dac6
bit5
Pll
Enable
[0]
ComDe
Lim0
BdGAp
Adj0
[0]
T_Slow
Ret1
RegNeg
Sleep
[1]
Dac6
bit4
Manual
[0]
Man
Com2
Man
Com1
Man
Com0
1
ComDe
Lim2
BdGap
Adj2
[0]
T_Slow
Ret3
Vcm
Sleep
[1]
Dac6
ToVCM
[0]
Speed
bit6
Dac12a
bit6
Dac12b
bit6
Watch
Dog3
VcmRet
SoftRis
Watch
Dog2
Vretract
2
Watch
Dog1
Vretract
1
Watch
Dog0
Vretract
0
2
3
T_Full
Power2
FlyBack
Slope1
T_Full
Power1
FlyBack
Slope0
T_Full
Power0
Shock
Thresh1
T_Slow
Ret5
Shock
Thresh0
T_Slow
Ret0
Shock
Sleep
[1]
Dac6
bit3
T_Vcm
Brake2
Spin
Sleep
[1]
Dac6
bit2
T_Vcm
Brake1
Reg3v3
Enable
[0]
Dac6
bit1
T_Vcm
Brake0
Temp
Select
[0]
Dac6
bit0
4
5
Speed
bit14
Speed
bit13
Speed
bit12
PllCur
1
6
Speed
bit11
Dac12a
bit11
Dac12b
bit11
Speed
bit10
Dac12a
bit10
Dac12b
bit10
Shock
Thresh2
[0]
Speed
bit9
Dac12a
bit9
Dac12b
bit9
Speed
bit8
Dac12a
bit8
Dac12b
bit8
Speed
bit7
Dac12a
bit7
Dac12b
bit7
Speed
bit5
Dac12a
bit5
Dac12b
bit5
Speed
bit4
Dac12a
bit4
Dac12b
bit4
Speed
bit3
Dac12a
bit3
Dac12b
bit3
Speed
bit2
Dac12a
bit
Dac12b
bit2
Speed
bit1
Dac12a
bit1
Dac12b
bit1
Speed
bit0
Dac12a
bit0
Dac12b
bit0
7
8
9
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