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參數(shù)資料
| 型號： | TDA4867J |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 偏轉 |
| 英文描述： | Full bridge current driven vertical deflection booster |
| 中文描述： | VERTICAL DEFLECTION IC, PZFM9 |
| 封裝： | PLASTIC, SOT-523-1, DIL-BENT-SIL, 9 PIN |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 426K |
| 代理商： | TDA4867J |
2003 Feb 05
6
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical
deflection booster
TDA4867J
THERMAL CHARACTERISTICS
Note
1.
To minimize the thermal resistance from mounting base to heatsink [R
th(mb-h)
] follow the recommended mounting
instruction: screw mounting preferred; torque = 40 Ncm; use heatsink compound; isolation plate increases R
th(mb-h)
.
CHARACTERISTICS
V
P
= 12 V; T
amb
= 25
°
C; V
FB
= 40 V; voltages referenced to ground (pin GND); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th(j-mb)
thermal resistance from junction to mounting base
note 1
4
K/W
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC supplies (pins V
P
and V
FB
)
V
P
V
FB
I
q(FB)
I
q(P)
Input stage (pins INP, INN and FEEDB)
supply voltage
flyback supply voltage
quiescent flyback current
quiescent supply current
8.2
V
P
+ 6
2.5
80
25
60
4
130
V
V
mA
mA
note 1
no load; no signal
I
defl
= 0
I
i(dif)
I
i(dif)(offset)
differential input current
differential input offset current
[I
i(dif)(offset)
= I
INP
I
INN
]
single-ended input current
input clamp voltage on pin INP
input clamp voltage on pin INN
feedback current
feedback voltage
note 2
I
defl
= 0; R
ref
= 3 k
;
R
m
= 1
0
±
500
±
600
±
20
μ
A
μ
A
I
INP,
I
INN
V
clamp(INP)
V
clamp(INN)
I
FEEDB
V
FEEDB
Output stages (pins OUTA and OUTB)
0
2.7
2.7
1
±
300
3.0
3.0
±
250
±
600
3.3
3.3
±
300
V
P
1
μ
A
V
V
μ
A
V
I
INP
= I
INN
= 0; note 3
I
INP
= I
INN
= 0; note 3
I
defl(p-p)
I
OUTA
, I
OUTB
V
sat(OUTA-GND)
deflection current (peak-to-peak value)
output current
saturation voltage pin OUTA to
pin GND
0.6
±
0.3
5.1
1.1
1.6
2.1
2.8
1.1
1.6
1.0
1.6
5.7
2.5
±
1.25
1.3
1.8
2.7
3.4
1.3
1.8
1.4
2.0
2
6.3
A
A
V
V
V
V
V
V
V
V
%
V
I
OUTA
= 0.7 A
I
OUTA
= 1.25 A; note 4
I
OUTA
= 0.7 A
I
OUTA
= 1.25 A; note 4
I
OUTB
= 0.7 A
I
OUTB
= 1.25 A; note 4
I
OUTB
= 0.7 A
I
OUTB
= 1.25 A; note 4
I
defl
=
±
0.7 A; note 5
I
i(dif)
= 0; closed loop
V
sat(VP-OUTA)
saturation voltage pin V
P
to pin OUTA
V
sat(OUTB-GND)
saturation voltage pin OUTB to
pin GND
V
sat(VP-OUTB)
saturation voltage pin V
P
to pin OUTB
LE
V
OUTA
, V
OUTB
linearity error
DC output voltage
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