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參數(shù)資料
| 型號： | TC9470FN |
| 元件分類： | DAC |
| 英文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 1-BIT DAC, PDSO24 |
| 封裝： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 377K |
| 代理商： | TC9470FN |
TC9470FN
2002-02-27
5
2. Data Input Circuit
DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge. It is consequently necessary for the DATA and LRCK signals to be
synchronized and input on the BCK signal falling edge as indicated in the timing example below. Also, as DATA has been designed so that the 16 bits before the
change point of LRCK are regarded as valid data, the data must be input with Right-justified mode when the BCK is 48 fs or 64 fs, as shown in Figure 2a.
Figure 2a Example of Input Timing Chart
L-ch
R-ch
LRCK
BCK
MSB 15
14
13
12
11
10
9
8
7
6
5
4
3
2
LSB MSB 15
14
13
12
11
10
9
8
7
6
5
4
3
2
LSB
DATA
Figure 2b Example of Input Timing Chart
Invalid data
L-ch
R-ch
LRCK
BCK
M
S
B
15 14 13 12 11 10 9 8 7 6 5 4 3 2
L
S
B
M
S
B
15 14 13 12 11 10 9 8 7 6 5 4 3 2
L
S
B
DATA
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