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參數(shù)資料
| 型號(hào)： | TC9444F |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP60 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-60 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TC9444F |
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TC9444F
2002-01-11
5
Block Operations
1.
Operating Clocks
The master clock can be selected between 5 2 or 384 fs using the CKS pin. The master clock uses
oscillator or external clock input, through the XI pin.
Regardless of a master clock, the number of digital signal processing steps are predetermined. However,
the DA converter’s operating clock varies according to the master clock mode.
The MCKS pin sets the MCKO output, selecting / or /2 divider of the XI pin.
Table 1.1
Operating Clock Selection and DA Converter Oversampling Rate
CKS Pin
MCKS Pin
XI Input
MCKO Output
DAC Oversampling Rate
L
192 fs
L
H
384 fs
192 fs
L
256 fs
H
512 fs
256 fs
2.
Digital Audio Data Input/Output
2.1
Sync Mode
The data input/output bit clock and internal sync (master) mode or external sync (slave) mode are
set using microcontroller interface bits SYNM and SYNM2. Initialization by reset sets master mode.
Table 2.1
Sync Mode and Input/Output Bit Clock Settings
SYNM2
SYNM1
SYNC Mode
BCKI
BCKO
0
Master
(Note 1)
64 fs
(Note 2)
0
1
Slave
32 fs
BCKI
1
0
Slave
48 fs
BCKI
1
Slave
64 fs
BCKI
Note 1: See Table 2.2.
Note 2: XI input divider clock
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相關(guān)代理商/技術(shù)參數(shù) |
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| TC9446F | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio |
| TC9446F-033 | 制造商:Panasonic Industrial Company 功能描述:IC |
| TC9446FG | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio |
| TC9447F | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Single-Chip Audio Digital Signal Processor |
| TC9452F | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:SINGLE CHIP SURROUND LSI |
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