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參數(shù)資料
| 型號： | TC90A53F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 3-LINE DIGITAL Y / C SEPARATOR IC |
| 中文描述： | 三線數(shù)碼Y /葷分離器集成電路 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 305K |
| 代理商： | TC90A53F |
TC90A53N/F
2001-02-08 10/17
AC CHARACTERISTICS
Y output
(Ta 25°C, V
DD
5 V, clock frequency 3.579545 MHz, 0.5 Vp-p, S1 2, VREF1
3.0 V)
CHARACTERISTIC
SYMBOL
TEST
CIR-
CUIT
TEST CONDITION
MIN
TYP.
MAX
UNIT
Input Level
V
IN
1
0~140 IRE ( Figure 2 )
1.5
1.6
V
p-p
Low-Frequency Gain
GV
1
S2 2, S3 2, S4 1, S5 2
V
IN
15.734 kHz,
1.5 V
p-p
Vdc 2.5 V
0.5
0.0
0.5
dB
MTF1
1
f2 / f1
2.0
1.2
0.5
Frequency Characteristics
MTF2
1
S2 2, S3 2,
S4 1, S5 2
V
IN
1.5 V
p-p
Vdc 2.5 V
f4 / f1
3.0
2.0
1.5
dB
Comb Characteristics
Comb
1
S2 2, S3 2,
S4 1, S5 2
V
IN
1.5 V
p-p
Vdc 2.5 V
f2 / f3
40
45
dB
L
s
1
Y1 / Y2
35
40
43
Linearity (Figure 1)
L
y
1
S2 1, S3 1,
S4 1, S5 2
V
IN
5-stage staircase
waveform,
1.5V
p-p
(Figure 2)
S / Y2
57
60
63
%
Output Impedance
Z
o
1
S2 1, S3 1, S5 2
V
IN
15.734 kHz, 1.5 V
p-p
Vdc 2.5 V
Zo
V1 : S4 1, V2 : S4 2
250
400
700
Clock Leakage
(4 f
sc
component)
L
ck
1
S2 2, S3 2, S4 1, S5 1
V
IN
No input
5.0
20
mV
rms
Clock Dominant Wave Leakag
(f
sc
component)
L
sc
1
S2 2, S3 2, S4 1, S5 1
V
IN
No input
1.0
2.0
mV
rms
400
V2
V2
V1
－
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