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參數(shù)資料
| 型號： | TC7107ACPLIJL |
| 元件分類： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, ACCESS, PDIP40 |
| 封裝： | CERDIP-40 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 269K |
| 代理商： | TC7107ACPLIJL |
9
TC7106
TC7106A
TC7107
TC7107A
3-1/2 DIGIT A/D CONVERTERS
When the TEST pin on the TC7106A is pulled to V+, all
segments are turned “ON.” The display reads –1888. During
this mode the LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
FOR MORE THAN SEVERAL MINUTES! LCD displays
may be destroyed if operated with DC levels for extended
periods.
The display font and the segment drive assignment are
shown in Figure 4.
DISPLAY FONT
1000's
100's
10's
1's
Figure 4. Display Font and Segment Assignment
In the TC7106A, an internal digital ground is generated
from a 6 volt zener diode and a large P channel source
follower. This supply is made stiff to absorb the large
capacitive currents when the backplane voltage is switched.
DIGITAL SECTION (TC7107A)
Figure 5 shows the TC7107A. It is designed to drive
common anode LEDs. It is identical to the TC7106A except
that the regulated supply and backplane drive have been
eliminated and the segment drive is typically 8mA. The
1000's output (pin 19) sinks current from two LED segments,
and has a 16mA drive capability.
In both devices, the polarity indication is “ON” for nega-
tive analog inputs. If V–
IN and V
+
IN are reversed, this indication
can be reversed also, if desired.
The display font is the same as the TC7106A.
System Timing
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The three-phase measure-
ment cycle takes a total of 4000 counts or 16000 clock
pulses. The 4000 count cycle is independent of input signal
magnitude.
Each phase of the measurement cycle has the following
length:
Auto-Zero Phase: 1000 to 3000 Counts
(4000 to 12000 Clock Pulses)
For signals less than full-scale, the auto-zero phase is
assigned the unused reference integrate time period.
Signal Integrate: 1000 Counts
(4000 Clock Pulses)
This time period is fixed. The integration period is:
TSI = 4000
Where fOSC is the externally set clock frequency.
Reference Integrate: 0 to 2000 Counts
(0 to 8000 Clock Pulses)
The TC7106A/7107A are drop-in replacements for the
7106/7107 parts. External component value changes are
not required to benefit from the low drift internal reference.
Clock Circuit
Three clocking methods may be used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An R-C oscillator using all three pins.
1
fOSC
Figure 6. Clock Circuits
COMPONENT VALUE SELECTION
Auto-Zero Capacitor – CAZ
The CAZ capacitor size has some influence on system
noise. A 0.47
F capacitor is recommended for 200mV full-
scale applications where 1 LSB is 100
V. A 0.047F capaci-
tor is adequate for 2.0V full-scale applications. A mylar
dielectric capacitor is adequate.
Reference Voltage Capacitor – CREF
The reference voltage used to ramp the integrator
output voltage back to zero during the reference-integrate
cycle is stored on CREF. A 0.1F capacitor is acceptable
when V–
IN is tied to analog common. If a large common-mode
voltage exists (V–
REF ≠ analog common) and the application
requires 200mV full-scale, increase CREF to 1.0 F. Rollover
error will be held to less than 1/2 count. A mylar dielectric
capacitor is adequate.
[]
TC7106A
TC7107A
4
CRYSTAL
RC NETWORK
40
38
EXT
OSC
39
÷
TO TEST PIN ON TSC7106A
TO GND PIN ON TSC7107A
TO
COUNTER
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