參數(shù)資料
型號(hào)： TC58DAM72A1FT00
廠商： Toshiba Corporation
英文描述： 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM
中文描述： 128兆位（16米x 8 BITS/8M x 16位）的CMOS NAND型E2PROM的
文件頁數(shù)： 16/34頁
文件大?。?/td> 369K
代理商： TC58DAM72A1FT00
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
2003-01-24 16/34
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs
are configured as shown in Figure 1.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the
operation mode command into the internal command
register. The command is latched into the command
register from the I/O port on the rising edge of the
WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading of either
address information or input data into the internal
address/data register.
Address information is latched on the rising edge of
WE
if ALE is High.
Input data is latched if ALE is Low.
Chip Enable:
The device goes into a low-power Standby mode when
CE
goes High during a Read operation. The
CE
signal is ignored when device is in Busy state (
such as during a Program or Erase operation, and will not enter Standby mode even if the
CE
input goes High.
The
CE
signal must stay Low during the Read mode Busy state to ensure that memory array data is correctly
transferred to the data register.
BY
/
RY
L),
Write Enable:
The
WE
signal is used to control the acquisition of data from the I/O port.
Read Enable:
The
RE
signal controls serial data output. Data is available t
REA
after the falling edge of
RE
.
The internal column address counter is also incremented (Address
Address l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the
device.
I/O Port: I/O9 to 16
The I/O9 to 16 pins are used as a port for input/output data to and from the device. The I/O9 to 16 pins are low
level(VIL) when address and command are asserted.
Write Protect:
The
WP
signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when
WP
is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
The
BY
/
RY
Busy state (
(
BY
/
RY
H) after completion of the operation. The output buffer for this signal is an open drain.
output signal is used to indicate the operating condition of the device. The
BY
/
RY
L) during the Program, Erase and Read operations and will return to Ready state
BY
/
RY
signal is in
NC
NC
NC
NC
NC
GND
BY
/
RY
RE
CE
NC
NC
V
CC
V
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vss
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
NC
NC
V
CCQ
NC
NC
NC
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
Vss
Figure 1 pinout
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