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參數(shù)資料
| 型號： | TC500 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | Precision Analog Front Ends |
| 中文描述： | 精密模擬前端 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 209K |
| 代理商： | TC500 |
3-25
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
0.01
0.1
1.0
N80
70
60
50
40
30
20
t = 0.1 sec
LINE FREQUENCY DEVIATION FROM 60 Hz (%)
NORMAL
MODE
REJECTION
DEV = DEVIATION FROM 60 Hz
t = INTEGRATION PERIOD
= 20 LOG
SIN 60 t (1
±
100
p
60
t (1
±
100
Figure 3. Line Frequency Deviation
Figure 4.. Integrating Converter Normal Mode Rejection
30
20
10
0
0.1/T
1/T
10/T
INPUT FREQUENCY
N
T = MEASUREMENT
PERIOD
1 t
INT
V
IN
(t) dt = V
REF
t
DEINT
R
INT
C
INT
0
R
INT
C
INT
where:
V
REF
= Reference Voltage
t
INT
= Signal Integration time (fixed)
t
DEINT
= Reference Voltage Integration time (variable)
For a constant V
IN
:
V
IN
= V
REF
t
DEINT
INT
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise spikes
are integrated (averaged to zero) during the integration
periods. Integrating ADCs are immune to the large conver-
sion errors that plague successive approximation convert-
ers in high-noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate. Interference
signals with frequencies at integral multiples of the integra-
tion period are, theoretically, completely removed since the
average value of a sine wave of frequency (1/t) averaged
over a period (t) is zero.
Integrating converters often establish the integration
period to reject 50/60Hz line frequency interference signals.
The ability to reject such signals is shown by a normal mode
rejection plot (Figure 4). Normal mode rejection is limited in
practice to 50 to 65dB, since the line frequency can deviate
by a few tenths of a percent (Figure 3).
TC500/500A/510/514 CONVERTER OPERATION
The TC500/500A/510/514 incorporates an Auto zero
and Integrator phase in addition to the input signal Integrate
and reference Deintegrate phases. The addition of these
phases reduce system errors and calibration steps, and
shorten overrange recovery time. A typical measurement
cycle uses all four phases in the following order:
(1) Auto zero
(2) Input signal integration
(3) Reference deintegration
(4) Integrator output zero
The internal analog switch status for each of these
phases is summarized in Table 1. This table is referenced
to the Functional Block Diagramon the first page of this data
sheet.
Auto-Zero Phase
(AZ)
During this phase, errors due to buffer, integrator and
comparator offset voltages are nulled out by charging C
AZ
(auto-zero capacitor) with a compensating error voltage.
The external input signal is disconnected from the
internal circuitry by opening the two SW
I
switches. The
internal input points connect to analog common. The refer-
ence capacitor is charged to the reference voltage potential
through SW
R
. A feedback loop, closed around the integrator
and comparator, charges the C
AZ
capacitor with a voltage to
compensate for buffer amplifier, integrator and comparator
offset voltages.
PRECISION ANALOG FRONT ENDS
TC500
TC500A
TC510
TC514
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TC500A | Precision Analog Front Ends |
| TC500ACPE | Precision Analog Front Ends |
| TC514COI | Precision Analog Front Ends |
| TC500CPE | PRECISION ANALOG FRONT ENDS |
| TC514CPJ | PRECISION ANALOG FRONT ENDS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC-500 | 制造商:Thomas & Betts 功能描述:COVER |
| TC500_06 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Precision Analog Front Ends |
| TC500_08 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Precision Analog Front Ends with Dual Slope ADC |
| TC50015A | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:ALUM ELECT/M: Capacitance: 150, Voltage: |
| TC50025A | 制造商:Mallory Sonalert Products Inc 功能描述:AXIAL LEADED ALUMINUM ELECTROLYTIC CAPACITORS 85 DGREE, HIGH RIPPLE, GENERAL PURPOSE CAPACITOR 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:ALUM ELECT/M: Capacitance: 250, Voltage: |
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