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參數(shù)資料
| 型號(hào)： | TC1321EUA |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 10-Bit Digital-to-Analog Converter with Two-Wire Interface |
| 中文描述： | 10位數(shù)字到模擬轉(zhuǎn)換器兩線接口 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 446K |
| 代理商： | TC1321EUA |
TC1321
DS21387B-page 8
2002 Microchip Technology Inc.
4.0
SERIAL PORT OPERATION
The Serial Clock input (SCL) and bi-directional data
port (SDA) form a 2-wire bi-directional serial port for
programming and interrogating the TC1321. The
following conventions are used in this bus architecture.
TABLE 4-1:
TC1321 SERIAL BUS
CONVENTIONS
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TC1321
always
operates as a Slave. The serial protocol is illus-
trated in Figure 3-1. All data transfers have two phases;
all bytes are transferred MSB first. Accesses are initi-
ated by a START condition (START), followed by a
device address byte and one or more data bytes. The
device address byte includes a Read/Write selection
bit. Each access must be terminated by a STOP Con-
dition (STOP). A convention called
Acknowledge
(ACK) confirms receipt of each byte. Note that SDA can
change only during periods when SCL is LOW (SDA
changes while SCL is HIGH are reserved for START
and STOP conditions).
4.1
START Condition (START)
The TC1321 continuously monitors the SDA and SCL
lines for a START condition (a HIGH to LOW transition
of SDA while SCL is HIGH), and will not respond until
this condition is met.
4.2
Address Byte
Immediately following the START condition, the host
must transmit the address byte to the TC1321. The
7-bit SMBus address for the TC1321 is
1001000
. The
7-bit address transmitted in the serial bit stream must
match for the TC1321 to respond with an Acknowledge
(indicating the TC1321 is on the bus and ready to
accept data). The eighth bit in the Address Byte is a
Read-Write bit. This bit is a 1 for a read operation or 0
for a write operation. During the first phase of any
transfer, this bit will be set = 0 to indicate that the
command byte is being written.
4.3
Acknowledge (ACK)
Acknowledge (ACK) provides a positive handshake
between the host and the TC1321. The host releases
SDA after transmitting eight bits, then generates a ninth
clock cycle to allow the TC1321 to pull the SDA line
LOW to Acknowledge that it successfully received the
previous eight bits of data or address.
4.4
Data Byte
After a successful ACK of the address byte, the host
must transmit the data byte to be written or clock out
the data to be read. (See the appropriate timing dia-
grams.) ACK will be generated after a successful write
of a data byte into the TC1321.
4.5
Stop Condition (STOP)
Communications must be terminated by a STOP con-
dition (a LOW to HIGH transition of SDA while SCL is
HIGH). The STOP condition must be communicated by
the transmitter to the TC1321. Refer to Figure 4-1, Tim-
ing Diagrams for serial bus timing.
Term
Explanation
Transmitter
Receiver
Master
The device sending data to the bus.
The device receiving data from the bus.
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP).
The device addressed by the master.
A unique condition signaling the beginning of
a transfer indicated by SDA falling
(High - Low) while SCL is high.
A unique condition signaling the end of a
transfer indicated by SDA rising (Low - High)
while SCL is high.
A Receiver Acknowledges the receipt of each
byte with this unique condition. The Receiver
drives SDA low during SCL high of the ACK
clock pulse. The Master provides the clock
pulse for the ACK cycle.
Communication is not possible because the
bus is in use.
When the bus is IDLE, both SDA and SCL will
remain high.
The state of SDA must remain stable during
the High period of SCL in order for a data bit
to be considered valid. SDA only changes
state while SCL is low during normal data
transfers. ( See START and STOP
conditions.)
Slave
START
STOP
ACK
Busy
Not Busy
Data Valid
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