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    參數(shù)資料
    型號(hào): TC1303B-FJ3EUNTR
    廠商: Microchip Technology Inc.
    英文描述: 500 mA Synchronous Buck Regulator, + 300 mA LDO with Power-Good Output
    中文描述: 500毫安同步降壓穩(wěn)壓器,300 mA的LDO具有電源就緒輸出
    文件頁數(shù): 20/30頁
    文件大?。?/td> 441K
    代理商: TC1303B-FJ3EUNTR
    TC1303B
    DS21949A-page 20
    2005 Microchip Technology Inc.
    As an example, for a 3.6V input, 1.8V output with a load
    of 400 mA, the efficiency taken from Figure 2-7 is
    approximately 84%. The internal power dissipation is
    approximately 171 mW.
    5.6.2
    LDO OUTPUT (V
    OUT2
    )
    The internal power dissipation within the TC1303B
    LDO is a function of input voltage, output voltage and
    output current. The following equation can be used to
    calculate the internal power dissipation for the LDO.
    EQUATION 5-7:
    The maximum power dissipation capability for a
    package can be calculated given the junction-to-
    ambient thermal resistance and the maximum ambient
    temperature for the application. The following equation
    can be used to determine the package’s maximum
    internal power dissipation.
    5.6.3
    LDO POWER DISSIPATION
    EXAMPLE
    5.7
    PCB Layout Information
    Some basic design guidelines should be used when
    physically placing the TC1303B on a Printed Circuit
    Board (PCB). The TC1303B has two ground pins, iden-
    tified as A
    GND
    (analog ground) and P
    GND
    (power
    ground). By separating grounds, it is possible to
    minimize the switching frequency noise on the LDO
    output. The first priority, while placing external compo-
    nents on the board, is the input capacitor (C
    IN1
    ). Wiring
    should be short and wide; the input current for the
    TC1303B can be as high as 800 mA. The next priority
    would be the buck regulator output capacitor (C
    OUT1
    )
    and inductor (L
    1
    ). All three of these components are
    placed near their respective pins to minimize trace
    length. The C
    IN1
    and C
    OUT1
    capacitor returns are con-
    nected closely together at the P
    GND
    plane. The LDO
    optional input capacitor (C
    IN2
    ) and LDO output capaci-
    tor C
    OUT2
    are returned to the A
    GND
    plane. The analog
    ground plane and power ground plane are connected
    at one point (shown near L
    1
    ). All other signals (SHDN1,
    SHDN2, feedback in the adjustable output case)
    should be referenced to A
    GND
    and have the A
    GND
    plane underneath them.
    FIGURE 5-1:
    Fixed 10-Pin MSOP.
    Component Placement,
    There will be some difference in layout for the 10-pin
    DFN package due to the thermal pad. A typical fixed-
    output DFN layout is shown below. For the DFN layout,
    the V
    IN1
    to V
    IN2
    connection is routed on the bottom of
    the board around the TC1303B thermal pad.
    FIGURE 5-2:
    Fixed 10-Pin DFN.
    Component Placement,
    Input Voltage
    V
    IN
    = 5V±10%
    LDO Output Voltage and Current
    V
    OUT
    = 3.3V
    I
    OUT
    = 300 mA
    Internal Power Dissipation
    P
    LDO(MAX)
    = (V
    IN(MAX)
    – V
    OUT(MIN)
    ) x I
    OUT(MAX)
    P
    LDO
    = (5.5V) – (0.975 x 3.3V))
    x 300 mA
    P
    LDO
    = 684.8 mW
    P
    LDO
    V
    IN MAX
    )
    )
    V
    OUT2 MIN
    )
    (
    )
    I
    OUT2 MAX
    )
    )
    ×
    =
    Where:
    P
    LDO
    = LDO Pass device internal
    power dissipation
    V
    IN(MAX)
    = Maximum input voltage
    V
    OUT(MIN)
    = LDO minimum output voltage
    TC1303B
    1
    2
    3
    6
    8
    7
    9
    10
    5
    4
    +V
    OUT1
    P
    GND
    +V
    IN1
    A
    GND
    A
    GND
    +V
    OUT2
    C
    OUT1
    C
    IN2
    C
    OUT2
    C
    IN1
    P
    GND
    Plane
    A
    GND
    Plane
    L
    1
    A
    GND
    to P
    GND
    +V
    IN2
    * C
    IN2
    Optional
    - Via
    1
    2
    3
    6
    8
    7
    9
    10
    5
    4
    +V
    OUT1
    P
    GND
    +V
    IN1
    A
    GND
    A
    GND
    +V
    OUT2
    C
    OUT1
    C
    IN2
    C
    OUT2
    C
    IN1
    P
    GND
    Plane
    A
    GND
    Plane
    L
    1
    A
    GND
    to P
    GND
    PGND
    *
    C
    IN2
    Optional
    +V
    IN2
    TC1303B
    - Via
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    參數(shù)描述
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    TC1303B-IA0EUN 功能描述:低壓差穩(wěn)壓器 - LDO PWM/LDO combo w/PG RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓(最大值):307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
    TC1303B-IA0EUNTR 功能描述:低壓差穩(wěn)壓器 - LDO PWM/LDO combo w/PG RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓(最大值):307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
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