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參數(shù)資料
| 型號： | TC1271RERCTR |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 4-Pin Reset Monitors |
| 中文描述： | 4引腳復(fù)位監(jiān)控器 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 609K |
| 代理商： | TC1271RERCTR |
TC1270/TC1271
DS21381D-page 6
2007 Microchip Technology Inc.
4.0
APPLICATIONS INFORMATION
4.1
V
CC
Transient Rejection
The
monitoring and Reset timing during power-up,
power-down, and brownout/sag conditions, and rejects
negative-going transients (glitches) on the power
supply line.
Figure 4-3
shows the maximum transient
duration vs. maximum negative excursion (overdrive)
for glitch rejection. Any combination of duration and
overdrive that lays
under
the curve will
not
generate a
Reset signal. Combinations above the curve are
detected as a brown-out or power-down. Transient
immunity can be improved by adding a capacitor in
close proximity to the V
CC
pin of the TC1270/TC1271.
TC1270/TC1271
provides
accurate
V
CC
FIGURE 4-1:
Duration vs. Overdrive for Glitch Rejection at
+25°C.
Maximum Transient
4.2
Reset Signal Integrity During
Power-Down
The TC1270 RESET output is valid to V
CC
= 1.0V.
Below this voltage the output becomes an “open circuit”
and does not sink current. This means CMOS logic
inputs to the microprocessor will be floating at an
undetermined voltage. Most digital systems are
completely shut down well above this voltage.
However, in situations where RESET must be
maintained valid to V
CC
= 0V, a pull-down resistor must
be connected from RESET to ground to discharge stray
capacitances and hold the output low (
Figure 4-2
). This
resistor value, though not critical, should be chosen
such that it does not appreciably load RESET under
normal operation (100 k
Ω
will be suitable for most
applications). Similarly, a pull-up resistor to V
CC
is
required for the TC1271 to ensure a valid high RESET
for V
CC
below 1.1V.
FIGURE 4-2:
V
CC
= 0V.
Ensuring RESET Valid to
4.3
Processors With Bidirectional
I/O Pins
Some microprocessor’s (such as Motorola 68HC11)
have bidirectional Reset pins. Depending on the
current drive capability of the processor pin, an indeter-
minate logic level may result if there is a logic conflict.
This can be avoided by adding a 4.7 k
Ω
resistor in
series with the output of the TC1270/TC1271
(
Figure 4-3
). If there are other components in the sys-
tem which require a Reset signal, they should be buff-
ered so as not to load the Reset line. If the other
components are required to follow the Reset I/O of the
microprocessor, the buffer should be connected as
shown with the solid line.
FIGURE 4-3:
Reset I/O.
Interfacing to Bidirectional
RESET COMPARATOR OVERDRIVE,
V
TH
- V
CC
(mV)
400
240
160
320
80
0
1
10
100
1000
M
T
A
= +25°C
V
TH
Duration
Overdrive
V
CC
TC127LMJ
TC127xR/S/T
TC1270
V
CC
V
CC
R1
100k
RESET
GND
TC1270
V
CC
RESET
GND
RESET
GND
Buffered RESET
To Other System
Components
Buffer
μ
P
4.7k
V
CC
V
CC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TC1271SERCTR | 4-Pin Reset Monitors |
| TC1271TERCTR | 4-Pin Reset Monitors |
| TC1270FERCTR | 4-Pin Reset Monitors |
| TC1270LERCTR | 4-Pin Reset Monitors |
| TC1270MERCTR | 4-Pin Reset Monitors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC1271SERC | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4-Pin レP Reset Monitors |
| TC1271SERCTR | 功能描述:監(jiān)控電路 4-Pin uP 2.93V Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TC1271TERC | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4-Pin レP Reset Monitors |
| TC1271TERCTR | 功能描述:監(jiān)控電路 4-Pin uP 38V Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TC1272 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:3-Pin Reset Monitors for 5V Systems |
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