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參數(shù)資料
| 型號(hào)： | TC1232EOE |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | MICROPROCESSOR MONITOR |
| 中文描述： | 微處理器監(jiān)控 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | TC1232EOE |
5-22
TELCOM SEMICONDUCTOR, INC.
V
CC
TOL GND
RST
ST
RESET
+5V
TC1232
TD
0.1
μ
F
10K
I/O
MICROPROCESSOR
3 -TERMINAL
REGULATOR
+5V
V
CC
TOL
PB RST
GND
RST
ST
I/O
MICROPROCESSOR
RESET
+5V
TC1232
TD
Figure 2. Watchdog Timer
Figure 1. Push-button Reset
mode and set it low while in the background or interrupt
mode. If both modes do not execute correctly, the watchdog
timer issues reset pulses.
Supply Monitor Noise Sensitivity
The TC1232 is optimized for fast response to negative-
going changes in V
DD
. Systems with an inordinate amount
of electrical noise on V
DD
(such as systems using relays),
may require a 0.01
μ
F or 0.1
μ
F bypass capacitor to reduce
detection sensitivity. This capacitor should be installed as
close to the TC1232 as possible to keep the capacitor lead
length short.
DETAILED DESCRIPTION
Power Monitor
The TC1232 detects out-of-tolerance power supply
conditions and warns a processor-based system of an
impending power failure. When V
CC
is detected as below the
preset level defined by TOL, the V
CC
comparator outputs the
signals RST and RST. If TOL is connected to ground, the
RST and RST signals become active as V
CC
falls below 4.75
volts. If TOL is connected to V
CC
, the RST and RST become
active as V
CC
falls below 4.5 volts. Because the processing
is stopped at the last possible moment of valid V
CC,
the RST
and RST are excellent control signals for a
μ
P. The reset
outputs will remain in their active states until V
CC
has been
continuously in-tolerance for a minimum of 250msec allow-
ing the power supply and
μ
P to stabilize before RST is
released.
Push-button Reset Input
The debounced manual reset input (PB RST) manually
forces the reset outputs into their active states. Once
PB RST has been low for a time t
PBD,
the push-button delay
time, the reset outputs go active. The reset outputs remain
in their active states for a minimum of 250msec after PB RST
rises above V
IH
(Figure
3).
A mechanical push-button or active logic signal can
drive the PB RST input. The debounced input ignores input
pulses less than 1msec and is guaranteed to recognize
pulses of 20msec or greater. No external pull-up resistor is
required
because the PB RST input has an internal pull-up
to
V
CC
of
approximately 100
μ
A.
Watchdog Timer
When the ST input is not stimulated for a preset time
period, the watchdog timer function forces RST and RST
signals to the active state. The preset time period is deter-
mined by the TD inputs to be 150msec with TD connected
to ground, 600msec with TD floating, or 1200msec with TD
connected to V
CC,
typical. The watchdog timer starts timing
out from the set time period as soon as RST and RST are
inactive. If a high-to-low transition occurs on the ST input pin
prior to time-out, the watchdog timer is reset and begins to
time-out again. If the watchdog timer is allowed to time-out,
then the RST and RST signals are driven to the active state
for 250msec minimum (Figure 2).
The software routine that strobes ST is critical. The code
must be in a section of software that is executed frequently
enough so the time between toggles is less than the watch-
dog time-out period. One common technique controls the
μ
P
I/O line from two sections of the program. The software
might set the I/O line high while operating in the foreground
TC1232
MICROPROCESSOR MONITOR
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