參數(shù)資料
型號(hào): TC1072
廠商: Microchip Technology Inc.
英文描述: 50mA and 100mA CMOS LDOs with Shutdown, ERROR Output and VREF Bypass
中文描述: 為50mA和100mA的CMOS低壓降穩(wěn)壓器具有關(guān)斷功能,錯(cuò)誤輸出和VREF繞道
文件頁(yè)數(shù): 11/12頁(yè)
文件大?。?/td> 126K
代理商: TC1072
TC1073
5
PRELIMINARY INFORMATION
TC1073-01 6/5/97
100mA CMOS LDO WITH SHUTDOWN,
ERROR OUTPUT AND V
REF
BYPASS
The following equation is used to calculate worst case
actualpower dissipation:
P
D
(V
INMAX
– V
OUTMIN
)I
LOADMAX
Where:
P
D
= Worst case actual power dissipation
V
INMAX
= Maximum voltage on V
IN
V
OUTMIN
= Minimum regulator output voltage
I
LOADMAX
= Maximum output (load) current
Equation 1.
The maximum allowable power dissipation (Equation 2)
is a function of the maximum ambient temperature (T
AMAX
),
the maximum allowable die temperature (125
°
C) and the
thermal resistance from junction-to-air (
θ
JA
). SOT-23A-6
packag has a
θ
JA
of approximately 220
°
C/Wattwhen
mounted on a single layer FR4 dielectric copper clad PC
board.
P
D MAX
= (T
JMAX
– T
JMAX)
θ
JA
Where all terms are previously defined.
Equation 2.
Equation 1 can be used in conjunction with Equation 2
to ensure regulator thermal operation is within limits. For
example:
Given:
V
INMAX
= 3.0V
±
10%
V
OUTMIN
= 2.7V
±
0.5V
I
LOAD
= 98mA
T
AMAX
= 55
°
C
Find:
1. Actual power dissipation
2. Maximum allowable dissipation
Actual power dissipation:
P
D
(V
INMAX
– V
OUTMIN
)I
LOADMAX
= [(3.0 x 1.1) – (2.7 x .995)]40 x 10
–3
= 60mW
Maximum allowable power dissipation:
P
DMAX
= (T
JMAX
– T
AMAX
)
θ
JA
= (125 – 55)
220
= 318mW
In this example, the TC1073 dissipates a maximum of
only 60mW; far below the allowable limit of 318mW. In a
similar manner, Equation 1 and Equation 2 can be used to
calculate maximum current and/or input voltage limits. For
example, the maximum allowable V
IN
is found by sustituting
the maximum allowable power dissipation of 318mW into
Equation 1, from which V
INMAX
= 5.9V.
Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads, and wide power
supply bus lines combine to lower
θ
JA
and therefore in-
crease the maximum allowable power dissipation limit.
相關(guān)PDF資料
PDF描述
TC1072-25VCH 50mA and 100mA CMOS LDOs with Shutdown, ERROR Output and VREF Bypass
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