參數(shù)資料
型號： TB310
廠商： Intersil Corporation
英文描述： Decimating Digital Filter
中文描述： 元氣，數(shù)字濾波
文件頁數(shù)： 17/19頁
文件大小： 190K
代理商： TB310
3-210
AC Electrical Specifications
V
CC
= +4.75V to +5.25V, T
A
= 0
o
C to 70
o
C
PARAMETER
SYMBOL
NOTES
-15
-25
-33
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
Input Clock Frequency
F
CK
F
FIR
t
CK
t
FIR
t
SPWL
t
SPWH
t
SK
0
15
0
25.6
0
33
MHz
FIR Clock Frequency
0
15
0
25.6
0
33
MHz
Input Clock Period
66
-
39
-
30
-
ns
FIR Clock Period
66
-
39
-
30
-
ns
Clock Pulse Width Low
26
-
16
-
13
-
ns
Clock Pulse Width High
26
-
16
-
13
-
ns
Clock Skew Between FIR_CK
and CK_IN
0
t
FIR
-25
0
t
FIR
-15
0
t
FIR
-15
ns
CK_IN Pulse Width Low
t
CH1L
t
CH1H
t
CIS
t
CIH
t
RSPW
t
RTRS
t
AST
t
STOD
t
STIC
t
SET
t
HOLD
t
WL
t
WH
t
STADD
Notes 5, 8
29
-
19
-
19
-
ns
CK_IN Pulse Width High
Notes 5, 8
29
-
19
-
19
-
ns
CK_IN Setup to FIR_CK
Notes 5, 8
27
-
17
-
17
-
ns
CK_IN Hold from FIR_CK
Notes 5, 8
2
-
2
-
2
-
ns
RESET Pulse Width Low
4t
CK
8t
CK
t
CK
+10
-
-
4t
CK
8t
CK
t
CK
+10
-
-
4t
CK
8t
CK
t
CK
+10
-
-
ns
Recovery Time on RESET
-
-
-
ns
ASTARTIN Pulse Width Low
-
-
-
ns
STARTOUT Delay from CK_IN
35
20
18
ns
STARTIN Setup to CK_IN
25
-
15
-
10
-
ns
Setup Time on DATA_IN
20
-
15
-
14
-
ns
Hold Time on All inputs
0
-
0
-
0
-
ns
Write Pulse Width Low
26
-
15
-
12
-
ns
Write Pulse Width High
26
-
20
-
18
-
ns
Setup Time on Address Bus Before
the Rising Edge of Write
26
-
20
-
20
-
ns
Setup Time on Chip Select Before the
Rising Edge of Write
t
STCS
26
-
20
-
20
-
ns
SetupTimeonControlBusBeforethe
Rising Edge of Write
t
STCB
26
-
20
-
20
-
ns
DATA_RDY Pulse Width Low
t
DRPWL
t
FIRDV
2t
FIR
-20
-
-
2t
FIR
-10
-
-
2t
FIR
-10
-
-
ns
DATA_OUT Delay Relative to
FIR_CK
50
35
28
ns
DATA RDY Valid Delay Relative
to FIR_CK
t
FIRDR
-
35
-
25
-
20
ns
DATA_OUT Delay Relative to
OUT_SELH
t
OUT
-
25
-
20
-
20
ns
Output Enable to Data Out Valid
t
OEV
t
OEZ
Note 6
-
15
-
15
-
15
ns
Output Disable to Data Out
Three-State
Note 5
-
15
-
15
-
15
ns
Output Rise, Output Fall Times
t
r
, t
f
from 0.8V to
2V, Note 5
-
8
-
8
-
6
ns
NOTES:
5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
6. Transition is measured at
±
200mV from steady state voltage with loading as specified in test load circuit with and C
L
= 40pF.
7. AC Testing is performed as follows: Input levels (CLK Input) 4.0V and 0V, Input levels (all other Inputs) 0V and 3.0V, Timing reference levels
(CLK) = 2.0V, (Others) = 1.5V, Output load per test load circuit and C
L
= 40pF.
8. Applies only when H_BYP = 1 or H_DRATE = 0.
HSP43220
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