參數(shù)資料
型號: TB28F004S5-100
廠商: INTEL CORP
元件分類: DRAM
英文描述: BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
中文描述: 512K X 8 FLASH 5V PROM, 100 ns, PDSO44
封裝: 13.30 X 28.20 MM, PLASTIC, SOP-44
文件頁數(shù): 31/37頁
文件大?。?/td> 611K
代理商: TB28F004S5-100
E
BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY
31
PRODUCT PREVIEW
V
Address Stable
Device
Address Selection
IH
V
IL
V
V
ADDRESSES (A)
IH
IL
V
IH
V
IL
V
V
CE# (E)
OE# (G)
Data
Valid
Standby
IH
IL
V
V
WE# (W)
DATA (D/Q)
(DQ0-DQ7)
OL
V
OH
High Z
Valid Output
High Z
IH
V
IL
V
RP# (P)
R1
R3
R4
R7
R6
R2
R5
R8
R9
R10
Figure 15. AC Waveform for Read Operations
6.2.5
COMMERCIAL TEMPERATURE RESET OPERATIONS
IH
V
IL
V
RP# (P)
IH
V
IL
V
RY/BY# (R)
P1
P2
Figure 16. AC Waveform for Reset Operation
#
Sym
Parameter
Notes
Min
Max
Unit
P1
t
PLPH
RP# Pulse Low Time
(If RP# is tied to V
CC
, this specification is not applicable)
100
ns
P2
t
PLRH
RP# Low to Reset during Block Erase, Program, or Lock-Bit
Configuration
2,3
12
μs
NOTES:
1.
2.
3.
These specifications are valid for all product versions (packages and speeds).
If RP# is asserted when the WSM is not busy (RY/BY# = ‘1’), the reset will complete within 100 ns.
A reset time, t
PHQV
, is required from the latter of RY/BY# or RP# going high until outputs are valid.
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