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參數(shù)資料
| 型號(hào)： | TB1262F |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA BiCMOS INTEGRATED CIRCUIT, SILICON MONOLITHIC |
| 中文描述： | 東芝的BiCMOS集成電路，硅單片 |
| 文件頁數(shù)： | 20/66頁 |
| 文件大?。?/td> | 1544K |
| 代理商： | TB1262F |
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TB1261F/TB1262F
2002-6-30 20 / 66
DEF]
V P
hase (00h)
Data
0
31
Vertical Position control by delaying the V-ramp timing
H Phase (10h)
[ Sub; 14h D4-D0 5 bits ]
Data
Descriptions
00
-3us
1F
3us
Horizontal Position control
V-Freq (000)
[ Sub; 15h D7
Data
Descriptions
000
Auto
001
50 Hz
010
60 Hz
011
50Hz in no input
100
Forced 312.5 H , stopped V pull-in
101
Forced 262.5 H , stopped V pull-in
110
Forced 313 H , stopped V pull-in
111
Forced 263 H , stopped V pull-in
Vertical frequency pull-in mode selection
AFC Gain
(00)
[ Sub; 18h D7
Data
Descriptions
00
Normal
01
1 / 3 sensitivity
10
X 3 at V blanking duration
11
AFC OFF
AFC gain
Sync gate (0)
[ Sub; 14h D7 1 bit ]
Data
Descriptions
0
Normal
1
Gated
F sync (0)
[ Sub; 14h D6 1 bit ]
Data
Descriptions
0
Normal ; for input from RF
1
F sync ; for input from AV
equipments
Forced sync
H S
TOP
(0)
[ Sub; 1Ch D6 1 bit ]
Data
Descriptions
0
Normal
1
& Y-mute & RGB mute; H STOP
H OUT stop
312/313
(0)
[ Sub; 14h D5 1 bit ]
Data
Descriptions
0
Normal
1
TELETXT(312/313)
(This function makes V-scanning non-interlace for
teletext)
[ Sub; 15h D4
Descriptions
(0H)
(31H)
D0 5 bits ]
D5 3 bits ]
D6 2 bits ]
VAGC (1)
Data
0
1
V Size (40h)
Data
00
01
7F
Vertical size alignment / Vstop
V Linearity (4h)
Data
Descriptions
0
-12 %
F
12 %
V linearity alignment
V cent.
(10h)
Data
Descriptions
0
-12 %
3F
12 %
V centering
VS Corr (4h)
Data
Descriptions
0
20 %
F
-12 %
V Ramp Ref. (0)
Data
Descriptions
0
External (YC Vcc)
1
Internal
Select the reference voltage
V.EHT
(0h)
Data
Descriptions
0
Min ( 0 %)
7
Max gain (-9 %)
Adjust the sensitivity for V
H Size (10)
Data
Descriptions
00
700 uA
3F
0 uA ( at top )
Adjust the H size by biasing the EW DC voltage
EW Para (40)
[ Sub; 1Bh D6-D0 7 bits ]
Data
Descriptions
00
0 uA(p-p)
7F
440 uA(p-p)
Adjust the EW Parabola amplitude
[ Sub; 1Bh D7 1 bit ]
Descriptions
Normal
Speed up (x3)
[ Sub; 16h D6D0 7 bits ]
Descriptions
V Stop
-47 %
47 %
[ Sub; 17h D7D4 4 bits ]
[ Sub; 18h D5
D0 6 bits ]
[ Sub; 17h D3D0 4 bits ]
[ Sub; 16h D7 1 bit ]
[ Sub; 1Eh D7
D5 3 bits ]
[ Sub; 1Ch D5-D0 5 bits ]
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