
www.ti.com ........................................................................................................................................................................................... SLOS570 – DECEMBER 2008
Table 2. Serial Control Interface Register Summary (continued)
NO. OF
INITIALIZATION
SUBADDRESS
REGISTER NAME
CONTENTS
BYTES
VALUE
0x34
ch2_bq[4]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x35
ch2_bq[5]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x36
ch2_bq[6]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x37 - 0x39
Reserved(3)
DRC ae(4)
u[31:26], ae[25:0]
0x0080 0000
0x3A
8
DRC (1 – ae)
u[31:26], (1 – ae)[25:0]
0x0000 0000
DRC aa
u[31:26], aa[25:0]
0x0080 0000
0x3B
8
DRC (1 – aa)
u[31:26], (1 – aa)[25:0]
0x0000 0000
DRC ad
u[31:26], ad[25:0]
0x0080 0000
0x3C
8
DRC (1 – ad)
u[31:26], (1 – ad)[25:0]
0x0000 0000
0x3D–0x3F
Reserved(2)
0x40
DRC-T
4
T[31:0] (9.23 format)
0xFDA2 1490
0x41
DRC-K
4
u[31:26], K[25:0]
0x0384 2109
0x42
DRC-O
4
u[31:26], O[25:0]
0x0008 4210
0x43–0x45
Reserved(2)
0x46
DRC control
4
Description shown in subsequent section
0x0000 0000
0x47–0x4F
Reserved(2)
0x50
Bank switch control
4
Description shown in subsequent section
0x0F70 8000
0x51–0xF8
Reserved(2)
0xF9
Update Device Address
4
u[31:8],New Dev Id[7:0] (New Dev Id = 0x38)
0x00000036
0xFA-0xFF
Reserved(2)
(3)
Reserved registers should not be accessed.
(4)
"ae" stands for
∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.
Note: All DAP coefficients are 3.23 format unless specified otherwise
Copyright 2008, Texas Instruments Incorporated
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