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參數(shù)資料
| 型號： | TAS5036BPFCR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Six Channel Digital Audio PWM Processor |
| 中文描述： | 六通道數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 14/58頁 |
| 文件大?。?/td> | 745K |
| 代理商： | TAS5036BPFCR |
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Architecture Overview
8
SLES073
—
February 2003
TAS5036B
2.1.3.1
Crystal Type and Circuit
In clock master mode the TAS5036B can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,
the TAS5036B uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5036B
as shown in Figure 2
–
1.
XO
TAS5036B
OSC
MACRO
rd
C1
XI
C2
AVSS
rd = Drive level control resistor
–
crystal vendor specified
CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)
CL = (C1 x C2 )/(C1 + C2 ) + CS (where CS = board stray capacitance ~ 3 pF)
Example: Vendor recommended CL = 18 pF, CS = 3 pF
≥
C1 = C2 = 2 x (18
–
3) = 30 pF
Figure 2
–
1. Crystal Circuit
2.1.4 Clock Slave Mode
In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5036B. The master
clock is supplied through the MCLK_IN terminal.
As in the master mode, the TAS5036B device develops its internal timing from the internal phase-locked loop
(PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a
frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data
sample rate. The LRCLK frequency is the data sample rate. The TAS5036B does not require any specific
phase relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5036B
monitors the relationship between MCLK, SCLK, and LRCLK. The TAS5036B detects if any of the three clocks
are absent, if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error,
or if the MCLK frequency is changing substantially with respect to the PLL frequency.
When a clock error is detected, the TAS5036B performs a clock error management sequence.
The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard
mute (PWM_P outputs are low; PWM_M outputs are high, and all VALID signals are low), resets all internal
processes, sets the volumes to mute, and suspends all I
2
C operations.
When the error condition is corrected, the TAS5036B exits the clock error sequence by performing a partial
re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in
the volume control registers. This sequence is performed over a 60 ms. interval. The TAS5036B preserves
all control register settings that were set prior to the clock interruption.
If a clock error occurs while the ERR_RCVRY terminal is asserted (low), the TAS5036B performs the error
management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with
the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering
a mute/unmute sequence by asserting and releasing MUTE either by using the terminal, the system control
register X01 D4, or the individual channel mute register D5
–
D0.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TAS5036BPFCRG4 | 功能描述:多媒體雜項 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
| TAS5036CPAG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5036IPFC | 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5036IPFCG4 | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5036IPFCR | 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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