參數(shù)資料
型號: TAS5036BPFCG4
廠商: Texas Instruments, Inc.
英文描述: Six Channel Digital Audio PWM Processor
中文描述: 六通道數(shù)字音頻PWM處理器
文件頁數(shù): 20/58頁
文件大小: 745K
代理商: TAS5036BPFCG4
Architecture Overview
14
SLES073
February 2003
TAS5036B
22
21
SCLK
24 Clks
LRCLK
Left Channel
19
1
0
19
1
0
MSB
24-Bit Mode
LSB
2-Channel Right-Justified Stereo Input/Output (24-Bit Transfer Word Size)
20
23
NOTE: All data presented in 2s complement form with MSB first.
1
0
8
9
15
14
18
18
8
9
8
9
15
14
15
14
22
21
24 Clks
Right Channel
19
1
0
19
1
0
MSB
LSB
20
23
1
0
8
9
15
14
18
18
8
9
8
9
15
14
15
14
20-Bit Mode
16-Bit Mode
Figure 2
8. Right-Justified 48-Fs Format
2.1.7.4
DSP Mode Timing
DSP mode timing uses an LRCLK to define when data is to be transmitted for both channels. A bit clock running
at 64
×
Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following
the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5036B masks unused trailing data bit positions.
SCLK
LRCLK
64 SCLKS
LSB
MSB
16 Bits
Left
Channel
16 Bits
Right
Channel
32 Bits Unused
SDIN
LSB
MSB
Figure 2
9. DSP Format
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參數(shù)描述
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