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Architecture Overview
17
SLES061B—November 2002—Revised January 2004
TAS5036A
Because PDN is an asynchronous control signal, small clicks and pops can be produced during the application
(the leading edge) of this control. However, when PDN is released, the transition from the hard mute state back
to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE should be applied before applying PDN.
2.2.3 General Status Register
The general status register is a read-only register. This register provides an indication when a volume update
is in progress or one of the channels is inactive. The device id can be read using this register.
Volume update is in progress—
Whenever a volume change is in progress due to a volume update
command or mute, this status bit is high.
Device identification code—
The device identification code 1 0 0 1 1 is displayed.
No internal errors (all valid signals are high)—
When there are no internal errors in the TAS5036A and all
outputs are valid, this status bit is high.
One or more valid signals are inactive—
If low, one or more channels of the TAS5036A are not outputting
data. The valid signals for those channels are inactive.
This can be produced by one of these causes:
If this signal is high, the TAS5036A is outputting data on all channels.
One or more of the clock signals are in error
ERROR recover is active (low)
The automute has silenced one or more channels that are receiving 0 inputs
MUTE has been set
Volume control has been set to full attenuation
2.2.4 Error Status Register
The error status register indicates historical information on control signal changes and clock errors. This
register latches these indications when they occur. The indications are cleared by writing 00h to the register.
This register is intended as a diagnostic tool to be used only when the system is not operating correctly. This
is because the error status bits are set when the data rate, serial data interface format, or master/slave mode
is changed. As a result, this register indicates an error condition even though the system is operating normally.
This register should only be used while diagnosing transient error conditions.
Any clock error or control signal terminal change which occurs since the last time the error status register was
cleared is displayed. In using this register, the first step is to initialize the device and verify that all of the clock
signals are active. Then this register should be cleared by writing 00h. After this point, the register indicates
any errors or control signal changes.
This register indicates an error condition by a high for the following conditions:
Fs error
A control terminal change has occurred (M_S, DBLSPD)
LRCLK error
MCLK_IN count error
DCLK phase error with respect to MCLK_IN
MCLK_IN phase error with respect to DCLK
PWM timing error
If all bits of the register are low, no errors have occurred and no control terminals changed.
There is no one-to-one correspondence of clock error indication to a system error condition. A particular
system error can be indicated by one or more error indications in this register. The system error conditions
and the reported errors are as follows: