
th1
tsu1
tpd1
tpd2
tsu2
th2
tc(SCLKIN)
SCLKIN
LRCLK
(Input)
SDOUT
SCLKOUT2
SDIN
tw(SCLKIN)
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SLES208B – JUNE 2009 – REVISED MARCH 2011
8.8
Serial Audio Port, Slave Mode
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
fLRCLK
Frequency, LRCLK (fS)
48
kHz
tw(SCLKIN)
Pulse duration, SCLKIN high
See (1)
0.4 tc(SCLKIN)
0.5 tc(SCLKIN)
0.6 tc(SCLKIN)
ns
fSCLKIN
Frequency, SCLKIN
See (2)
64 FS
MHz
Propagation delay, SCLKIN falling edge to
tpd1
16
ns
SDOUT
tsu1
Setup time, LRCLK to SCLKIN rising edge
10
ns
th1
Hold time, LRCLK from SCLKIN rising edge
5
ns
tsu2
Setup time, SDIN to SCLKIN rising edge
10
ns
th2
Hold time, SDIN from SCLKIN rising edge
5
ns
Propagation delay, SCLKIN falling edge to
tpd2
15
ns
SCLKOUT2 falling edge
(1)
Period of SCLKIN = TSCLKIN = 1/fSCLKIN
(2)
Duty cycle is 50/50.
Figure 8-4. Serial Audio Port Slave Mode Timing Waveforms
Copyright 2009–2011, Texas Instruments Incorporated
Electrical Specifications
41