
Block Header 1
I2C EEPROM Memory Map
M004001
Data Block 1
Block Header 2
Data Block 2
w
Block Header N
Data Block N
SLES208B – JUNE 2009 – REVISED MARCH 2011
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The TAS3202 uses the master mode to download from EEPROM the memory contents for the
microprocessor program memory, microprocessor extended memory, audio DSP core program memory,
audio DSP core coefficient memory, and audio DSP core data memory.
The TAS3202, when operating as an I2C master, can execute a complete download of any internal
memory or any section of any internal memory without requiring any wait states.
The TAS3202 generates a repeated start without an intervening stop command while downloading
program and memory data from EEPROM. When a repeated start is sent to the EEPROM in read mode,
the EEPROM enters a sequential read mode to transfer large blocks of data quickly.
The TAS3202 queries the bus for an I2C EEPROM at address 1010xxx. The value xxx can be chip select,
other information, or don’t cares, depending on the EEPROM selected.
The first action of the TAS3202 as master is to transmit a start condition along with the device address of
the I2C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the
address byte, and the TAS3202 sends a subaddress byte, which the EEPROM acknowledges. Most
EEPROMs have at least 2-byte addresses and acknowledge as many as are appropriate. At this point, the
EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3202 acknowledges each
byte repeatedly to continue reading each data byte that is stored in memory.
The memory load information starts with reading the header and data information that starts at
subaddress 0 of the EEPROM. This information must then be stored in sequential memory addresses with
no intervening gaps. The data blocks are contiguous blocks of data that immediately follow the header
locations.
The TAS3202 memory data can be stored and loaded in (almost) any order. Additionally, this addressing
scheme permits portions of the TAS3202 internal memories to be loaded.
Figure 6-6. EEPROM Address Map
26
Microprocessor Controller
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