TAPC640
High-Speed Switching ATM Port Controller (APC)
Product Brief
August 2000
2
Lucent Technologies Inc.
Features
(continued)
I
Implements a flexible, efficient buffer/congestion
management scheme based on a Bell Labs’ pat-
ented adaptive dynamic thresholding (ADT) algo-
rithm:
— Supports selective cell discard and early/partial
packet discard (EPD/PPD).
— Provides capability for minimum buffer reserva-
tions on per-connection, per-class, and per-port
basis.
I
Performs ATM Forum-compliant available bit rate
(ABR) explicit rate flow control using a Bell Labs’ pat-
ented algorithm. Provides optional support for EFCI
marking as well.
I
Provides operations, administration, and mainte-
nance (OA&M) Fault Management functions for loop-
back, continuity check, defect indication on all
connections, and performance monitoring on up to
127 connections.
I
Can be used in conjunction with an external switch
fabric (LUC4AS01 (ASX) and LUC4AC01 (ACE) ICs,
part of the high-speed switching chip set) to provide
a scalable, nonblocking switch solution for over
100 Gbits/s capacity.
I
Supports bandwidth scalability to OC-48 rates via
use of external PIMUX devices on the PHY layer
side.
I
Provides an enhanced services interface (ESI) to
support operation of an optional external adjunct
device for comprehensive statistical data collection.
I
Facilitates circuit board testing with on-chip IEEE
*
boundary scan.
I
Fabricated as a low-power, monolithic IC in submi-
cron 0.25
μ
m, 3.3 V CMOS technology, with 5 V tol-
erant and TTL-level compatible I/O.
I
Available in a 600-pin LBGA package.
Applications
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ATM switches
I
x-DSL systems
I
DLC systems
I
ADM
I
Access multiplexers
I
Routers
I
PBX
I
Wireless infrastructure equipment
I
VP rings
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.