參數(shù)資料
型號(hào)： TA1316AN
廠商： Toshiba Corporation
英文描述： YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV
中文描述： YCbCr /色差信號(hào)處理器和同步數(shù)字電視，逐行掃描電視和雙掃描電視
文件頁(yè)數(shù)： 24/115頁(yè)
文件大小： 1399K
代理商： TA1316AN
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TA1316AN
2002-10-04
24
Bus Control Functions
Write Mode
Parameter
Explanation
Preset
H-FREQUENCY
Selects horizontal oscillation frequency.
00: 15.75 kHz, 01: 31.5 kHz, 10: 33.75 kHz, 11: 45 kHz
Control by pin 22 has priority over BUS control. When this IC will be used on CRT,
the frequency of H-out should be controlled by pin 22.
33.75 kHz
H-DUTY
Switches horizontal output duty.
0: 41%, 1: 47%
41%
YUV-SW
Switches YUV input.
0: INPUT-1 (Y1/C
b1
/C
r1
), 1: INPUT-2 (Y2/C
b2
/C
r2
)
INPUT-1
DAC 1
Switches DAC control output.
Don't use this function
Open
DAC 2
Switches DAC control output.
0: On (low), 1: Open (high)
When TEST
=
00, controls 1-bit DAC when output is open-collector.
When TEST
=
01, outputs ACB reference pulse from pin 36.
On
SYNC INPUT-SW
Selects sync input.
00: Selects HD1/VD1 input.
01: Selects HD2/VD2 input.
10/11: Selects SYNC input.
HD/VD1
HORIZONTAL
POSITION
Adjusts horizontal picture phase.
0000000 (
10.5%)~1111111 (
+
10.5%)
(Note) When H-POSITION will be changed, VP width (pin 27) will change.
Center
CLP-PHS
Switches clamp pulse phase.
0: 0.7-
μ
s (2.5%) width with 1.1-
μ
s (3.8%) delay from HD stop phase
1: 0.7-
μ
s (2.4%) width with 0.2-
μ
s (0.7%) delay from HD stop phase
While quiescent, 0.8-
μ
s (2.7%) width with 1.2-
μ
s (4.2%) delay from FBP start
phase
Also switches CP phase of SCP-OUT (pin 18).
1.1-
μ
s delay
ACB MODE
Sets ACB mode. Selects reference level for convergence.
00: ACB off (cutoff BUS control), 01: ACB on (5 IRE),
10: ACB on (10 IRE), 11: ACB on (20 IRE)
ACB on (10 IRE)
SCP-SW
Switches SCP (sandcastle pulse) mode.
0: Internal mode, 1: External input mode
Also switches SCP-OUT (pin 18).
(Note) Don’t use H-BPP for the timing pulse, because H-BPP width of internal
mode will be changed by the temperature.
Inside IC
HBP-PHS
Switches horizontal black peak detection pulse phase.
0:
±
6.3% of FBP, 1:
±
3.5% of FBP
6.3% width
SYNC SEP-LEVEL
Selects SYNC separation level.
00: 8.5%, 01: 20%, 10: 30%, 11: 40%
min
TEST
Test mode
When TEST
=
00, controls 1-bit DAC when output is open-collector.
When TEST
=
01, outputs H-SYNC from pin 28 and ACB reference pulse from pin
36.
Do not use TEST
=
10/11 because this is used for IC Shipment Test mode.
00
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