
Lucent Technologies Inc.
3
Preliminary Data Sheet
July 2000
T8535/T8536 Quad Programmable Codec
Table of Contents
(continued)
Figures
Page
Figure 1. Functional Block Diagram, Each Section...................................................................................................5
Figure 2. 44-Pin PLCC Pin Diagram .........................................................................................................................7
Figure 3. 68-Pin PLCC Pin Diagram .........................................................................................................................9
Figure 4. 100-Pin TQFP Pin Diagram .....................................................................................................................11
Figure 5. 64-Pin TQFP Pin Diagram .......................................................................................................................13
Figure 6. Command Frame Format, Master to Slave, Read or Write Commands..................................................17
Figure 7. Command Frame Format, Slave to Master, Read Commands................................................................17
Figure 8. Write Operation, Normal Mode (Continuous DCLK)................................................................................18
Figure 9. Write Operation, Normal Mode (Gapped DCLK) .....................................................................................18
Figure 10. Write Operation, Byte-by-Byte Mode (Continuous DCLK).....................................................................19
Figure 11. Write Operation, Byte-by-Byte Mode (Gapped DCLK) ..........................................................................19
Figure 12. Read Operation, Normal Mode (Continuous DCLK)..............................................................................20
Figure 13. Read Operation, Normal Mode (Gapped Clock)....................................................................................21
Figure 14. Read Operation, Byte-by-Byte Mode (Continuous DCLK).....................................................................22
Figure 15. Read Operation, Byte-by-Byte Mode (Gapped DCLK) ..........................................................................23
Figure 16. Fast Scan, Normal Mode (Continuous DCLK).......................................................................................24
Figure 17. Fast Scan, Normal Mode (Gapped DCLK) ............................................................................................25
Figure 18. Fast Scan, Byte-by-Byte Mode (Continuous DCLK)..............................................................................26
Figure 19. Fast Scan, Byte-by-Byte Mode (Gapped DCLK) ...................................................................................26
Figure 20. Hardware Reset Procedure ...................................................................................................................27
Figure 21. Internal Signal Processing .....................................................................................................................29
Figure 22. Serial Interface Timing, Normal Mode (One Byte Transfer Shown).......................................................39
Figure 23. Byte-by-Byte Mode Timing.....................................................................................................................39
Figure 24. Single-Clocking Mode (TXBITOFF = 0, RXBITOFF = 0, PCMCTRL2 = 0x00)......................................41
Figure 25. Single-Clocking Mode (TXBITOFF = 1, RXBITOFF = 2, PCMCTRL2 = 0x01)......................................41
Figure 26. Double-Clocking Mode (Bit Offset = 0, PCMCTRL2 = 0x00).................................................................43
Figure 27. POTS Interface ......................................................................................................................................48