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參數(shù)資料
| 型號(hào)： | T8100A |
| 廠商： | Lineage Power |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)間段交換機(jī)) |
| 中文描述： | H.100/H.110接口和時(shí)隙交換器（H.100/H.110接口和干線時(shí)間段交換機(jī)） |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | T8100A |
2
Lucent Technologies Inc.
Product Brief
May 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100A
Description
(continued)
Onboard clock circuitry, including a digital phase-locked loop, supports all H.100/H.110 clock modes including
MVIP and SC-bus compatibility clocks. The local CHI interfaces support PCM rates of 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s. The AmbassadorT8100A has internal circuitry to support either minimum
latency or multi-time-slot frame integrity. Frame integrity is a requisite feature for applications that switch wideband
data (ISDN H-channels). Minimum latency is advantageous in voice applications.
5-6101(F)x
Figure 1. Block Diagram of the Ambassador
…
…
…
H.100/H.110, H-MVIP MVIP SC-BUS
INTERNAL
CLOCKS AND
STATE
COUNTER
S/P AND P/S CONVERTERS
256
LOCATION
DATA
SRAM
THREE 256
LOCATION
CONNECTION
CAMs
1024
LOCATION
DATA
MEMORY
OUTPUT
LOGIC
AND P/S
CONVERT
INPUT
LOGIC
AND S/P
CONVERT
1024
LOCATION
CONNECTION
MEMORY
TIMING AND
CONTROL
MICROPROCESSOR
INTERFACE
FRAME GROUP
INTERFACE
LOGIC
FRAME
GROUPS
ADDR[1:0]
DATA[7:0]
μ
P CONTROLS
MISC. I/O
CLOCKS AND REFS
INTERNAL
DATA
INTERNAL
ADDRESS
AND
CONTROL
LOCAL OUT
LOCAL IN
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