參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 97/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
97
Lucent Technologies Inc.
Facility Data Links
(continued)
Facility Data Link Parameter/Status Registers
(continued)
The following registers report the status of the FDL/HDLC and are read only.
Table 105. FDL Fill Status Register (FDL_SR0)
Table 106. FDL Receiver Status Register (FDL_SR1)
Table 107. FDL Receiver ANSI ESF Bit Codes (FDL_SR2)
Table 108. Receiver FDL FIFO Access Register (FDL_SR3)
Bits
0
Description
Receiver Full (RF).
This bit is set to 1 when the receive FIFO is at or above the programmed full level
(see register FDL_PR1). This status bit is cleared to 0 by a read of register FDL_SR3 (register 07).
Receive End of Frame (REOF).
This bit is set to 1 when the receiver has finished receiving a frame. It
becomes 1 upon reception of the last bit of the closing flag of a frame or the last bit of an abort sequence.
This status bit is cleared to 0 by a read of this register. This bit is not generated in the transparent mode.
Receiver Overrun (ROVERUN).
This bit is set to 1 when the receive FIFO has overrun its capacity. This
status bit is cleared to 0 by a read of this register.
Receiver Idle (RIDL).
This bit is set to 1 when the receiver is idle (i.e., 15 or more consecutive 1s have
been received). This status bit is cleared to 0 by a read of this register.
Receive ANSI Bit Codes (RANSI).
This bit is set to 1 when the FDL receiver recognizes a valid T1.403
ESF FDL bit code. The receive ANSI bit code is stored in register FDL_SR2. This status bit is cleared to 0
by a read of this register.
Reserved.
Must be set to 0.
1
2
3
4
5—7
Bits
0—6
Description
Receive Queue Status (RQS[0:6]).
Bits 0—6 indicate how many bytes are in the receive FIFO, including
the first status of frame (SF) byte. The bits are encoded in binary where bit 0 is the least significant bit.
End of Frame (EOF).
When
EOF = 1 the receive queue status indicates the number of bytes up to and
including the first SF byte.
7
Bits
0—5
Description
RANSI[0:5].
This register contains bits X0X1X2X3X4X5 of the ESF FDL bit messages of the following
form: 0X
5
X
4
X
3
X
2
X
1
X
0
0 11111111. These bits are cleared to 3F when a clear-on-read occurs.
Reserved.
6—7
Bits
0—7
Description
DATA0—DATA7.
The user data received via the FDL receiver are read through this register.
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