- 您現(xiàn)在的位置：買賣IC網 > PDF目錄383876 > T7290A (Lineage Power) DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口) PDF資料下載
參數(shù)資料
| 型號： | T7290A |
| 廠商： | Lineage Power |
| 英文描述： | DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口) |
| 中文描述： | DS1/T1/CEPT/E1線路接口（DS1/T1/CEPT/E1線接口） |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 420K |
| 代理商： | T7290A |
Data Sheet
April 1998
T7290A DS1/T1/CEPT/E1 Line Interface
14
Lucent Technologies Inc.
Alarms and Maintenance
(continued)
Jitter Attenuator Alarm (ESA)
A jitter attenuator alarm (ESA = 1) is indicated if the
phase jitter exceeds the tolerance of the jitter attenua-
tor. Bit errors occur when ESA is active. This signal is
asserted until error-free operation resumes. See
Figure 9 to determine the tolerance limits of the attenu-
ator.
Transmitter Short Circuit
A transmitter monitor is provided to detect nonfunction-
ing links and protect the device from damage. If one of
the transmitter's line drivers (T2 or R2) is shorted to the
power supply or ground, or if T2 and R2 are shorted
together, internal circuitry protects the device from
damage. After 35 transmit clock cycles, the transmitter
is powered up in its normal operating mode. The drivers
attempt to correctly transmit the next data bit (+1, 0, or
–1). If the short is still present, the transmitter is again
internally protected for 35 transmit clock cycles. This
process is continuously repeated until the short has dis-
appeared. The TSC alarm is not available off-chip.
AIS (Blue Signal) Generator
When the transmit blue signal is set (TBS = 1), a contin-
uous stream of bipolar 1s is transmitted onto the line
synchronous with EXCLK. The TPDATA and TNDATA
inputs are ignored during this mode. If the IN-LOS
output is externally connected to the TBS input, an
IN-LOS error initiates a transmit blue signal as long as
IN-LOS = 1. Also, TBS input is ignored when a remote
loopback is selected. There is no microprocessor inter-
face for the TBS input, i.e., any change on the TBS pin
is fed directly into the device and is not impeded by the
CS function.
Loopbacks
The T7290A device has three independent loopback
paths, which are activated as shown in Table 7.
A local loopback (LP1) connects the jitter attenuator's
output clock and data to the receive clock and data out-
put pins. MODE1:2 = 01 must be selected for this loop-
back to operate (jitter attenuator in the transmit path).
Valid transmit output data continues to be sent to the
network. However, if the transmit blue is initiated
(TBS = 1), an all-1s signal is sent to the network and
does not corrupt the looped data. The IN-LOS alarm still
monitors the entire receive function.
A remote loopback (LP2) loops the recovered clock and
retimed data into the transmitter and back onto the line.
The receive front end, receive PLL, jitter attenuator (if
engaged), and transmit driver circuitry are all exercised.
The transmit clock, transmit data, and TBS inputs are
ignored. Valid receive output data continues to be sent
to RPDATA and RNDATA. This loop can be used to isolate
failures between systems.
A digital local loopback (LP3) directly loops the transmit
clock and data to the receive clock and data output pins.
The blue signal can be transmitted when in this loopback.
LP3 (rather than LP1) must be selected if MODE2 = 0.
Table 7. Loopback Control
* TBS is ignored.
Microprocessor Interface
A chip-select input (CS) configures the device in either
hardware mode or microprocessor mode. The chip-select
function applies to the following inputs: MODE1, MODE2,
EC1, EC2, EC3, LOOPA, and LOOPB. In the hardware
mode, any change on these asynchronous input pins is
fed directly into the device. To maintain hardware mode,
set CS = 0. In the microprocessor mode, new digital con-
trol inputs are loaded into the T7290A device on the fall-
ing edge of CS and are latched on the rising edge of CS.
Figure 11 shows a timing diagram of this function.
Note that there are special requirements only when using
microprocessor mode. For example, the state of the input
should not change while CS = 0. Also, the state of the
internal latch is undefined (unknown to the user) until the
first falling edge of CS is encountered.
In-Circuit Testing
The device has the ability to allow for in-circuit testing by
activating the high-impedance mode (TRI = 0). During
this mode, all output buffers (T2, R2, RCLK, RPDATA,
RNDATA, IN-LOS, ESA, and OUT-LOS) are 3-stated.
During the 3-stated condition, the absolute maximum
voltage ratings must not be exceeded on any pin.
Operation
Symbol LOOPA
—
LP3
LP2*
LP1
LOOPB
0
1
0
1
Normal
Digital Local Loopback
Remote Loopback
Local Loopback
0
0
1
1
相關PDF資料 |
PDF描述 |
|---|---|
| T7295-1 | E3 Integrated Line Receiver(E3 集成線接收器) |
| T7295-6 | DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器) |
| T7296 | Integrated Line Transmitter(集成PCM線傳送器) |
| T7502 | Dual PCM Codec with Filters(帶濾波器的雙PCM編解碼器) |
| T7503 | Dual PCM Codec with Filters(帶濾波器的雙PCM編解碼器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T-7290A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T7290A DS1/T1/CEPT Line Interface |
| T-7290A-EL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T7290A DS1/T1/CEPT Line Interface |
| T-7290A--EL | 制造商:Alcatel-Lucent 功能描述:DATACOM, PCM TRANSCEIVER, PDSO28 |
| T7290A-EL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:T7290A DS1/T1/CEPT Line Interface |
| T-7290A--EL-DT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。