參數(shù)資料
型號: T7288
廠商: Lineage Power
英文描述: CEPT/E1 Line Interface(CEPT/E1 線接口)
中文描述: CEPT/E1線路接口(CEPT/E1線接口)
文件頁數(shù): 11/22頁
文件大?。?/td> 432K
代理商: T7288
Data Sheet
January 1998
T7288 CEPT/E1 Line Interface
11
Lucent Technologies Inc.
Overview
(continued)
Digital Logic
(continued)
Table 4. Rail Interface and Logic Mode Options
* Default operation (identical with LC1135B) if both pins are unconnected.
X = illegal option.
Table 5. Single-Rail Operation (Default State)
SR
/DR = 0 (or left unconnected internal pull-down circuitry).
Table 6. Dual-Rail Operation
SR
/DR = 1.
Alarms
An independent loss of clock (
LOC
) output is provided so that loss of clock is detected when the shutdown option is
in effect.
LOS
and
LOC
can be wire-ORed to produce a single alarm.
A bipolar violation output is included if HDB3 = 0, giving an alarm (VIO) each time a violation occurs (two or more
successive 1s on a rail). The violation alarm output is held in a latch for one cycle of the internal clock (RCLK). In
the HDB3 mode, HDB3 code violations are detected and an alarm is produced.
An alarm test pin (
ALMT
) is provided to test the alarm outputs,
LOS
,
LOC
, and VIO. Clearing this pin forces the
alarm outputs to the alarm state without affecting data transmission.
FLM
0*
0
1
1
SR
/DR
0*
1
0
1
Single-/Dual-Rail
Single
Dual
X
Dual
Logic Mode
1
1
X
2
Pin
3
4
6
8
Name
Function
HDB3/TNDATA
VIO/RNDATA
RDATA/RPDATA
TDATA/TPDATA
HDB3 enable as in the LC1135B device
VIO violation as in the LC1135B device
RDATA receive data as in the LC1135B device
TDATA transmit data as in the LC1135B device
Pin
3
4
6
8
Name
Function
HDB3/TNDATA
VIO/RNDATA
RDATA/RPDATA
TDATA/TPDATA
N-rail transmit input data
N-rail receive output data
P-rail receive output data
P-rail transmit input data
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