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| 型號(hào)： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 33/116頁(yè) |
| 文件大小： | 1056K |
| 代理商： | T7234A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
29
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 11. Control Flow State Machine Status (Address 07h)
Reg
CFR1
R/W
R
Bit 7
I4I
Bit 6
AIB
Bit 5
FEBE
Bit 4
NEBE
Bit 3
UOA
Bit 2
OOF
Bit 1
XACT
Bit 0
ACTR
Register
CFR1
Bit
0
Symbol
ACTR
Name/Description
Receive Activation.
Follows act bit in receive U-interface data stream.
0—Pending activation.
1—Ready to transmit.
U-Transceiver Active.
0—Transceiver not active.
1—Transceiver starting up or active.
Out of Frame.
0—U-interface out of frame.
1—Normal.
U-Interface Only Activation.
Follows uoa bit in receive U-interface data
stream.
CFR1
1
XACT
CFR1
2
OOF
CFR1
3
UOA
0—U-interface only for activation.
1—U-interface and S/T-interface for activation.
Near-End Block Error.
Follows nebe bit in receive U-interface data
stream.
0—CRC error detected in previously received U frame.
1—No error.
Far-End Block Error.
Follows febe bit in receive U-interface data
stream.
CFR1
4
NEBE
CFR1
5
FEBE
0—Error detected at LT.
1—No error.
Alarm Indication Bit.
Follows aib in receive U-interface data stream.
CFR1
6
AIB
0—Failure of intermediate 2B+D transparent element.
1—Transmission path established between LT and NT.
INFO 4 Indicator.
CFR1
7
I4I
0—Non-INFO 4.
1—INFO 4.
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