![](http://datasheet.mmic.net.cn/390000/SYM53C180_datasheet_16836330/SYM53C180_25.png)
Interface Signal Descriptions
2-7
logic also provides the necessary drive, sense thresholds, and input
hysteresis to function correctly in a SCSI bus environment.
The SYM53C180 receives data and parity signals and passes them from
the source bus to the load bus and provides any necessary edge shifting
to guarantee the skew budget for the load bus. Either side of the
SYM53C180 may be the source bus or the load bus. The side that is
asserting, deasserting, or releasing the SCSI signals is the source side.
These steps describe the SYM53C180 data processing:
1.
Asserted data is accepted by the receiver logic as soon as it is
received. Once the clock signal (REQ/ACK) has been received, data
is gated from the receiver latch.
2.
The path is next tested to ensure the signal if being driven by the
SYM53C180 is not misinterpreted as an incoming signal.
3.
The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The duration is
controlled by the input signal.
4.
The next stage uses a latch to sample the signal. This provides a
stable data window for the load bus.
5.
The final step develops pull-up and pull-down controls for the SCSI
I/O logic, including 3-state controls for the pull-up.
6.
A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
2.1.7.2 SCSI Bus Activity LED (BSY_LED)
Internal logic detects SCSI bus activity and generates a signal that
produces an active HIGH output. This output can be used to drive a LED
to indicate SCSI activity.
The internal circuitry is a digital one shot that is an active HIGH with a
minimum pulse width of 16 ms. The BSY_LED output current is 8 mA.
This output may have an LED attached to it with the other lead of the
LED grounded through a suitable resistor.