參數(shù)資料
型號(hào): SY89871U
廠商: Micrel Semiconductor,Inc.
英文描述: 2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/ FANOUT BUFFER WI/INTERNAL TERMINATION
中文描述: 2.5GHz的任何微分。在對(duì)可編程的LVPECL時(shí)鐘分頻器/扇出緩沖器威斯康星/內(nèi)部終端
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 168K
代理商: SY89871U
5
Precision Edge
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
TIMING DIAGRAM
V
IN
Swing
/RESET
IN
/IN
/QB
QB
QA
/QA
t
PD
t
RR
V
CC/2
V
OUT
Swing
V
CC
= 3.3V
±
10% or 2.5V
±
5%; T
A
=
40
°
C to +85
°
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Output Toggle Frequency
Output Swing
400mV
2.5
GHz
Maximum Input Frequency
Note 12
3.2
GHz
t
PLH
t
PHL
Differential Propagation Delay
Input Swing < 400mV
460
580
710
ps
IN-to-QA or QB
Input Swing
400mV
420
550
670
ps
t
SKEW
Within-Device Skew (Differential)
QB0-to-QB1
Note 13
7
15
ps
Within-Device Skew (Differential)
QA-to-QB
Note 13
12
30
ps
Part-to-Part Skew (Differential)
Note 13
250
ps
T
jitter
Cycle-to-Cycle Jitter
Note 14
1
ps
rms
ps
pp
ps
Total Jitter
Note 15
10
t
RR
t
r
,
t
f
Reset Recovery Time
600
Output Rise/Fall Times
(20% to 80%)
70
150
250
ps
Notes:
11. Measured with 400mV input signal, 50% duty cycle, all loading with 50
to V
CC
2V, unless otherwise stated.
12. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output
÷
2,
÷
4,
÷
8,
÷
16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
13. Skew is measured between outputs under identical transitions.
14. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
jitter_cc
=T
n
T
n+1
,
where T is the time between rising edges of the output signal.
15. Total jitter definition: with an ideal clock input, of frequency
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS
(11)
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