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參數(shù)資料
| 型號： | SY89858UMGTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PRECISION LOW POWER 1:8 LVPECL FANOUT BUFFER WITH INTERNAL TERMINATION |
| 中文描述： | 89858 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, MLF-32 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 956K |
| 代理商： | SY89858UMGTR |
Micrel
SY89858U
November 2004
M9999-110504
hbwhelp@micrel.com
or (408) 955-1690
3
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY89858UMG
MLF-32
Industrial
SY89858 with Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY89858UMGTR
(2)
MLF-32
Industrial
SY89858 with Pb-Free bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals Only.
2. Tape and Reel.
Pin Configuration
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 3130 29 28 27 26 25
VCC
GND
IN
VT
VREF-AC
/IN
GND
VCC
GND
VCC
Q3
/Q3
Q4
/Q4
VCC
GND
/
Q
/
Q
V
Q
/
V
Q
/
Q
/
V
/
Q
V
32-Pin MLF (MLF-32)
Pin Description
Pin Number
Pin Name
Pin Function
3, 6
IN, /IN
Differential Input: This differential input accepts AC- or DC-coupled signals as
small as 100mV (200mV
pp
). Each pin of this pair internally terminates to a VT
pin
through 50 . Note that these inputs will default to an indeterminate state if left
open. Please refer to the “Input Interface Applications” section for more details.
4
VT
Input Termination Center-Tap: Each side of the differential input pair terminates
to this VT
pin. The VT pin provides a center-tap to a termination network for
maximum interface flexibility. See the “Input Interface Applications” section for
more details.
5
VREF-AC
Reference Voltage: This output biases to V
CC
–1.2V (typical). It is used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01uF low ESR capacitor to V
CC
. Maximum sink/source
capability is 1.5mA.
1, 8, 9, 16, 18,
23, 25, 32
VCC
Positive Power Supply: Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors as close
to the VCC pins as possible.
31, 30, 29, 28,
27, 26, 22, 21,
20, 19, 15, 14,
13, 12, 11, 10
Q0, /Q0, Q1,
/Q1, Q2, /Q2,
Q3, /Q3, Q4,
/Q4, Q5, /Q5,
Q6, /Q6, Q7,
/Q7
100k LVPECL Differential Outputs: Differential buffered output copy of the input
signal. The LVPECL output swing is typically 800mV into 50
Unused output pairs may be left floating with no impact on jitter. See “LVPECL
Output” section.
to V
CC
–2V.
2, 7, 17, 24
GND
Exposed Pad
Ground: Ground pins and exposed pad must be connected to the same ground
plane.
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