參數(shù)資料
型號: SY89845UMGTR
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: PRECISION CML RUNT PULSE ELIMINATOR 2:1 MUX WITH 1:2 FANOUT AND INTERNAL TERMINATION
中文描述: 89845 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, QCC24
封裝: 4 X 4 MM, LEAD FREE, MLF-24
文件頁數(shù): 4/18頁
文件大?。?/td> 608K
代理商: SY89845UMGTR
Micrel, Inc.
SY89845U
May 2005
M9999-052405
hbwhelp@micrel.com
or (408) 955-1690
4
Pin Description
Pin Number
Pin Name
Pin Function
5, 2
23, 20
IN0, /IN0,
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV
(200mV
pp
). Each pin of a pair internally terminates to a VT
pin through 50
.
Please refer to the “Input Interface Applications” section for more details.
3, 21
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to V
CC
–1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01μF low ESR capacitor to VCC. Due to the limited drive
capability, the VREF-AC pin is only intended to drive its respective VT pin.
Maximum sink/source current is ±1.5mA. Please refer to the “Input Interface
Applications” section for more details.
4, 22
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. Please refer to the “Input Interface Applications”
section for more details.
1, 6, 9, 10
13, 19, 24
VCC
Positive Power Supply: Bypass with 0.1μF||0.01μF low ESR capacitors as close
to the VCC pins as possible.
7, 8, 11, 12
Q0, /Q0
Q1, /Q1
Differential Outputs: These differential CML outputs are a logic function of the
IN0, IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
15
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k
pull-up resistor
and will default to logic HIGH state if left open.
14, 17, 18
GND,
Exposed Pad
Ground: Ground and exposed pad must be connected to the same ground plane.
16
CAP
Power-On Reset (POR) initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure
the internal RPE logic starts up in a known state. See “Power-On Reset (POR)
Description” section for more details regarding capacitor selection. If this pin is
tied directly to VCC, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. The CAP pin should never be left open.
Truth Table
Inputs
IN1
Outputs
Q
IN0
/IN0
/IN1
SEL
/Q
0
1
X
X
0
0
1
1
0
X
X
0
1
0
X
X
0
1
1
0
1
X
X
1
0
1
1
0
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