參數(shù)資料
型號(hào): SY89840UMG
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: Precision LVPECL Runt Pulse Eliminator 2:1 Multiplexer
中文描述: 89840 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, QCC16
封裝: LEAD FREE, MLF-16
文件頁(yè)數(shù): 7/15頁(yè)
文件大?。?/td> 1745K
代理商: SY89840UMG
Micrel, Inc.
SY89840U
February 2005
7
M9999-021705
hbwhelp@micrel.com
or (408) 955-1690
AC Electrical Characteristics
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to + 85°C, R
L
= 50 to V
CC
–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
Clock
100mV
<
V
IN
200mV
(8)
200mV
<
V
IN
800mV
(8)
1.5
2.0
GHz
480
625
880
ps
460
600
820
ps
RPE enabled, see Timing Diagram
17
cycles
t
pd
Differential Propagation Delay In-to-Q
In-to-Q
SEL-to-Q
SEL-to-Q
RPE disabled (V
IN
= V
CC
/2)
550
900
ps
t
pd
Tempco
Differential Propagation Delay
Temperature Coefficient
115
fs/
o
C
t
SKEW
Part-to-Part Skew
Note 9
200
ps
Note 10
1
ps
(rms)
Note 11
1
ps
(rms)
Random Jitter
Cycle-to-Cycle Jitter
Total Jitter (TJ)
Note 12
10
ps
(pp)
t
Jitter
Crosstalk-induced Jitter
Note 13
0.7
ps
(rms)
t
r,
t
f
Output Rise/Fall Time (20% to 80%)
At full output swing
70
130
190
ps
Notes:
7.
8.
9.
High-frequency AC-parameters are guaranteed by design and characterization.
Propagation delay is measured with input t
r
, t
f
300ps (20% to 80%) and V
IL
800mV.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
10. Random jitter is measured with a K28.7 character pattern, measured at <f
MAX
.
11. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n
– T
n-1
where T is the time between rising edges of the
output signal.
12. Total jitter definition: with an ideal clock input of frequency <f
MAX
, no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
13. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
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