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參數(shù)資料
| 型號(hào)： | SY89834UMITR |
| 廠商： | MICREL INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V/3.3V TWO INPUT , 1GHz LVTTL/CMOS-TO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR |
| 中文描述： | 89834 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, MLF-16 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | SY89834UMITR |
4
PRELIMINARY
Precision Edge
SY89834U
Micrel
V
CC
= 2.5V
±
5% or 3.3V
±
10%, T
A
=
–
40
°
C to +85
°
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
t
PLH
t
PHL
t
SW
t
SKEW
Maximum Frequency
Input t
r
/ t
f
≥
350ps,
Note 2
Note 4
1.0
GHz
Propagation Delay (IN1, IN2-to-Q)
200
320
500
ps
Switchover Time (SEL-to-Q)
200
320
500
ps
Within-Device Skew
Note 5
5
20
ps
Part-to-Part Skew
300
ps
t
JITTER
Cycle-to-Cycle Jitter
Total Jitter
Note 6
Note 7
1
1
ps(rms)
ps(pk-pk)
DC
Duty Cycle
Input t
r
/t
f
≥
350ps,
Note 8
Note 9 and Note 10
45
50
55
%
t
S
t
H
t
r
,
t
f
Set-Up Time (EN to IN1, IN2)
300
ps
Hold Time (EN to IN1, IN2)
Note 9 and Note 10
500
ps
Output Rise/Fall Times
(20% to 80%)
70
140
225
ps
Note 1.
Note 2.
Note 3.
Note 4.
Measured with a 2.0V input signal, 50% duty cycle, all PECL loading with 50
to V
CC
–
2V. Output swing is
≥
400mV.
Specification for packaged product only.
f
MAX
is defined as the maximum input frequency while enduring a valid output. f
MAX
is limited by the input stage.
V
= 2.0V, V
= 0.8V, 50% duty cycle. Delay measured at 100MHz from the crossing of the input signal with V
CC
/2 as the crossing of the
differential output signal. See Figure 1.
Skew is measured between outputs under identical transitions.
Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs.
T
JITTER_CC
= T
n
–
T
n+1
, where T is the time between rising edges of the output signal.
Total jitter definition: with an ideal clock input frequency of
≤
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
If t
r
/t
f
is less than 350ps, the duty cycle distortion will increase beyond the duty cycle limits.
Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applica-
tions set-up and hold times do not apply.
Note 10.
See
“
Timing Diagrams,
”
Figure 1a.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
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| SY89835U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V, 2GHz (3.2 Gbps) Ultra-Precision, Differential 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input |
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| SY89835UMGTR | 制造商:Micrel Inc 功能描述:2GHz Diff. 1:2 LVDS Fanout Buffer MLF8 |
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