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參數(shù)資料
| 型號： | SY89825UHI |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5/3.3V 1:22 HIGH-PERFORMANCE, LOW-VOLTAGE PECL BUS CLOCK DRIVER & TRANSLATOR w/ INTERNAL TERMINATION |
| 中文描述： | 89825 SERIES, LOW SKEW CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 59K |
| 代理商： | SY89825UHI |
2
ClockWorks
SY89825U
Micrel
LOGIC SYMBOL
CLK_SEL
LVDS_CLK
/LVDS_CLK
LVPECL_CLK
/LVPECL_CLK
OE
0
1
22
22
Q0 - Q21
/Q0 - /Q21
LEN
D
Q
Pin
Function
LVDS_CLK,
/LVDS_CLK
Differential LVDS Inputs
(Internal 100
termination included)
Differential LVPECL Inputs.
LVPECL_CLK,
/LVPECL_CLK
CLK_SEL
Input CLK Select (LVTTL)
OE
Output Enable (LVTTL)
Q
0
–
Q
21
, /Q
0
–
/Q
21
Differential LVPECL Outputs.
Terminate with 50
to V
CC
-2V
Ground
GND
V
CCI
Power Supply. Connect to
V
CC
on PCB. V
CCI
and V
CCO
are not
internally connected
V
CCO
Power Supply for Output Buffer.
Connect to V
CCI
on PCB. V
CCI
and
V
CCO
are not internally connected
PIN NAMES
OE
(1)
CLK_SEL
Q
0
–
Q
21
LOW
/Q
0
–
/Q
21
HIGH
0
0
0
1
LOW
HIGH
1
0
LVDS_CLK
/LVDS_CLK
1
1
LVPECL_CLK
/LVPECL_CLK
TRUTH TABLE
NOTE:
1. The OE (output enable) signal is synchronized with the low level of the
LVDS_CLK and LVPECL_CLK signal.
Signal
I/O
Level
LVDS_CLK, /LVDS_CLK
Input
LVDS
Q
0
–
Q
21
, /Q
0
–
/Q
21
LVPECL_CLK, /LVPECL_CLK
Output
LVPECL
Input
LVPECL
CLK_SEL, OE
Input
LVCMOS/LVTTL
SIGNAL GROUPS
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.
Symbol
Rating
Value
Unit
V
CCI
/ V
CCO
V
IN
I
OUT
Tstore
θ
JA
V
CC
Pin Potential to Ground Pin
Input Voltage
–
0.5 to +4.0
V
–
0.5 to V
CCI
–
50
V
DC Output Current
mA
Storage Temperature
Package Thermal Resistance (Junction-to-Ambient)
With exposed pad soldered to GND
–
65 to +150
°
C
–
Still-Air (multi-layer PCB)
–
200lfpm (multi-layer PCB)
–
500lfpm (multi-layer PCB)
–
Still-Air (multi-layer PCB)
–
200lfpm (multi-layer PCB)
–
500lfpm (multi-layer PCB)
23
18
15
44
36
30
4.3
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
Exposed pad notsoldered to GND
θ
JC
Package Thermal Resistance
(Junction-to-Case)
相關PDF資料 |
PDF描述 |
|---|---|
| SY89825U | 2.5/3.3V 1:22 HIGH-PERFORMANCE, LOW-VOLTAGE PECL BUS CLOCK DRIVER & TRANSLATOR w/ INTERNAL TERMINATION |
| sy89833l | 3.3V, 2GHz ANY-DIFFERENTIAL INPUT-TO-LVDS 1:4 FANOUT BUFFER/TRANSLATOR W/ INTERNAL TERMINATION |
| SY89834U | 2.5V/3.3V TWO INPUT , 1GHz LVTTL/CMOS-TO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR |
| SY89834UMI | 2.5V/3.3V TWO INPUT , 1GHz LVTTL/CMOS-TO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR |
| SY89834UMITR | 2.5V/3.3V TWO INPUT , 1GHz LVTTL/CMOS-TO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SY89825UHITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5/3.3V 1:22 HIGH-PERFORMANCE, LOW-VOLTAGE PECL BUS CLOCK DRIVER & TRANSLATOR w/ INTERNAL TERMINATION |
| SY89825UHY | 功能描述:轉換 - 電壓電平 3.3V 1:22 LVDS Fanout/Translator (I Temp, Lead Free) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY89825UHY TR | 功能描述:轉換 - 電壓電平 3.3V 1:22 LVDS Fanout/Translator (I Temp, Lead Free) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY89825UHYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5/3.3V 1:22 HIGH-PERFORMANCE, LOW-VOLTAGE PECL BUS CLOCK DRIVER & TRANSLATOR w/ INTERNAL TERMINATION |
| SY898265UHI | 制造商:Micrel Inc 功能描述: |
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