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參數(shù)資料
| 型號： | SY89546UMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX 4:1 LVDS DIFF 2.5V 32-MLF |
| 標準包裝： | 1,000 |
| 系列： | SY89 |
| 類型： | 多路復用器 |
| 電路： | 1 x 4:1 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY89546UMGTR SY89546UMGTR-ND |
Micrel, Inc.
SY89546U
April 2011
7
M9999-0041911-B
hbwhelp@micrel.com
AC Electrical Characteristics
(10)
VCC = 2.5V± 5%; -40°C≤ TA ≤ +85°C, RL = 100 across Q and /Q, unless stated otherwise.
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
Gbps
fMAX
Maximum Operating Frequency
VOUT ≥ 200mV
Clock
3
4
GHz
IN-to-Q
330
430
530
ps
tPD
Differential Propagation Delay
SEL-to-Q
200
400
700
ps
Note 11
4
20
ps
Note 12
8
20
ps
tSKEW
Input-to-Input Skew
Output-to- Output Skew
Part-to-Park Skew
Note 13
200
ps
Note 14
1
psRMS
Data
Random Jitter (RJ)
Deterministic Jitter (DJ)
Note 15
10
psPP
Note 16
10
psPP
tJITTER
Clock
Total Jitter (TJ)
Cycle-to-Cycle Jitter
Note 17
1
psRMS
Crosstalk
Crosstalk-Induced Jitter
Note 18
0.7
psRMS
tr, tf
Output Rise/Fall Time
(20% to 80%)
At full output swing
35
80
150
ps
Notes:
1. Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High frequency AC parameters are guaranteed by
design and characterization.
2. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew
does not include the output skew.
3. Output-to-output skew is measured between two different outputs under identical input transitions.
4. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
5. Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
6. Deterministic jitter is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 2
23–1 PRBS pattern.
Total jitter definition: with an ideal clock input of frequency ≤ f
MAX
, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
7. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T-T
n-1
where T is the time between rising edges of the output cycle.
8. Crosstalk is measured at the output while applying two similar clock frequencies to adjacent inputs that are asynchronous with respect to each other
at the inputs.
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| SY89546UMI | 功能描述:IC MUX 4:1 LVDS DIFF 2.5V 32MLF RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復用器，解碼器 系列:SY89 標準包裝:25 系列:74HC 類型:解碼器 電路:1 x 2:4 獨立電路:2 輸出電流高，低:5.2mA，5.2mA 電壓電源:單電源 電源電壓:2 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-DIP 包裝:管件 |
| SY89546UMI TR | 功能描述:IC MUX 4:1 LVDS DIFF 2.5V 32-MLF RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復用器，解碼器 系列:SY89 標準包裝:25 系列:74HC 類型:解碼器 電路:1 x 2:4 獨立電路:2 輸出電流高，低:5.2mA，5.2mA 電壓電源:單電源 電源電壓:2 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-DIP 包裝:管件 |
| SY89546UMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION |
| SY89547L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with 1:2 FANOUT and INTERNAL TERMINATION |
| SY89547L_09 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with 1:2 FANOUT and INTERNAL TERMINATION |
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