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參數(shù)資料
| 型號： | SY89542UMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX 2:1 LVDC DUAL 2.5V 32MLF |
| 標準包裝： | 1,000 |
| 系列： | SY89 |
| 類型： | 多路復用器 |
| 電路： | 1 x 2:1 |
| 獨立電路： | 2 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 帶卷 (TR) |
5
Precision Edge
SY89542U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
V
CC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100 across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
NRZ Data
3.2
Gbps
V
OUT > 200mV
Clock
4
GHz
t
pd
Differential Propagation Delay
IN-to-Q
250
350
450
ps
SEL-to-Q
200
350
600
ps
t
SKEW
Input-to-Input Skew
Note 11
20
ps
Bank-to-Bank Skew
Note 12
25
ps
Part-to-Part Skew
Note 13
200
ps
t
JITTER
Data
Random Jitter (RJ)
Note 14
1ps
RMS
Deterministic Jitter (DJ)
Note 15
10
ps
PP
Clock
Total Jitter (TJ )
Note 16
10
ps
PP
Cycle-to-Cycle Jitter
Note 17
1ps
RMS
Crosstalk-Induced Jitter
Note 18
0.7
ps
RMS
t
r, tf
Output Rise / Fall Time
At full output swing
35
80
150
ps
(20% to 80%)
Notes:
10. Measured with 100mV input swing. See “Timing Diagrams ” section for definition of parameters. High frequency AC-parameters are guaranteed by
design and characterization.
11. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew
does not include the output skew.
12. Bank-to-bank skew is the difference in time from input to the output between banks.
13. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
14. Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
15. Deterministic jitter is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 223–1 PRBS pattern.
16. Total jitter definition: with an ideal clock input of frequency ≤ fMAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
17. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal.
18. Crosstalk is measured at the output while applying two similar frequencies to adjacent inputs that are asynchronous with respect to each other at the
inputs.
AC ELECTRICAL CHARACTERISTICS(10)
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| SY89542UMI | 功能描述:IC MUX 2:1 LVDC DUAL 2.5V 32MLF RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復用器，解碼器 系列:SY89 標準包裝:25 系列:74HC 類型:解碼器 電路:1 x 2:4 獨立電路:2 輸出電流高，低:5.2mA，5.2mA 電壓電源:單電源 電源電壓:2 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-DIP 包裝:管件 |
| SY89542UMI TR | 功能描述:IC MUX 2:1 DIFF DUAL 2.5V 32-MLF RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復用器，解碼器 系列:SY89 標準包裝:25 系列:74HC 類型:解碼器 電路:1 x 2:4 獨立電路:2 輸出電流高，低:5.2mA，5.2mA 電壓電源:單電源 電源電壓:2 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-DIP 包裝:管件 |
| SY89542UMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5Vm 3.2Gbps DUAL, DIFFERENTIAL 2:1 LVDS MULTIPLEXER WITH INTERNAL TERMINATION |
| SY89543L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 3.2Gbps DUAL, DIFFERENTIAL 2:1 LVDS MULTIPLEXER with INTERNAL TERMINATION |
| SY89543L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 3.2Gbps DUAL, DIFFERENTIAL 2:1 LVDS MULTIPLEXER with INTERNAL TERMINATION |
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