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參數(shù)資料
| 型號： | SY89538LHG |
| 廠商： | MICREL INC |
| 元件分類： | 其它接口 |
| 英文描述： | 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 628K |
| 代理商： | SY89538LHG |
Micrel, Inc.
Pin Description
Power
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
4
Pin Number
Pin Name
Pin Function
1
VCCA
Analog PLL Power Pin. Connects to “quiet” 3.3V supply. 3.3V power pins must be
connected together on the PCB. Bypass with 0.1μF//0.01μF low ESR capacitors and
place them as close to the VCCA pin as possible.
6, 56
VCCD
Digital Logic Core Power Pin. VCCD connects to a 3.3V supply. All power pins must
be connected together on the PCB. Bypass with 0.1μF//0.01μF low ESR capacitors
and place them as close to the VCCD pin as possible.
19, 40, 43, 51
VCCO
LVDS and LVPECL Output Driver Power Pins. These outputs can be powered from a
2.5V or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V ±10% or
2.5V ±5%. All power pins must be connected together on the PCB. Bypass with
0.1μF//0.01μF low ESR capacitor and place them as close to the VCCO pin as
possible.
15
GNDA
Analog PLL Ground. Connect to “quiet” ground. GNDA and GND must be connected
together on the PCB.
16, 30, 31,
47, 55
GND,
Exposed Pad
Ground: GND pins and exposed pad must both be connected to the same ground
plane.
Control and Configuration
Pin Number
Pin Name
Pin Function
62
LR
Analog Input/Output. Provides the reference voltage for the PLL loop filter and is
used with the LF pin. See “External Loop Filter Considerations” for recommended
loop filter values.
63
LF
Analog Input/Output. Provides the loop filter node for the PLL. See “External Loop
Filter Considerations” for recommended loop filter values.
2, 7
RSEL1, RSEL0
TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inputs.
The two-bit input pre-scalar divides the input reference frequency by /1, /2, /4, or /8.
RSEL0 is the LSB bit. See “Reference Input Divider and Zero Delay MUX Divider
Select Table” for proper decoding. The threshold voltage V
TH
= V
CC
/2. Internal 25k
pull-up. The default logic is HIGH.
10
INSEL
TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input.
Internal 25k
pull-up. The default is logic HIGH, and selects the XTAL input. The
threshold voltage V
TH
= V
CC
/2.
Logic HIGH: XTAL Select
Logic LOW: Reference Input Select
36
LSEL
TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL,
DSEL, and LEN are used together to decode the selection and post divider of the
LVDS outputs. Internal 25k
pull-up. See “LVDS Output Post-Divider and Frequency
Select Table” for proper decoding. The threshold voltage V
TH
= V
CC
/2. The default
logic is HIGH.
37
LEN
TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and acts as
a frequency select pin. LEN, DSEL, and LSEL are used together to decode the
selection and post divide of the LVDS output bank, see the “LVDS Output Post-
Divider and Frequency Select Table” for proper decoding. Internal 25k
pull-up.
When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are
HIGH. The threshold voltage V
TH
= V
CC
/2. The default logic is HIGH.
TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx,
DSEL and PENx are used together to decode the selection and post divider of the
PECL outputs. PSELx pins include an internal 25k
pull-up. The threshold voltage
V
TH
= V
CC
/2. See "LVPECL Output Post-Divider and Frequency Select Table” for
proper decoding.
23
25
57
59
PSEL0
PSEL1
PSEL2
PSEL3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89538LHG TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
| SY89538LHH | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHH TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHY | 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Lead Free) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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