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參數(shù)資料
| 型號(hào)： | SY89534LHZ |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 15/15頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZR LVPECL OUT 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:13 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-EP-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2087 SY89534LHZ-ND |
9
Precision Edge
SY89534/35L
Micrel, Inc.
M9999-110308
hbwhelp@micrel.com or (408) 955-1690
REFCLK Input Interface
The flexible REFCLK inputs are designed to accept any
differential to single-ended input signal within 300mV above
VCC and 300mV below ground.
Do not leave unused REFCLK inputs floating. Tie either the
true or complement inputs to ground, but not both. A logic zero
is achieved by connecting the complement input to ground
with the true input floating. For a TTL input, tie a 2.5k
resistor
between the complement input and ground. See “Input
Interface” section, Figures 4a through 4j.
Input Levels
LVDS, CML and HSTL differential signals may be connected
directly to the REFCLK inputs. Depending on the actual worst
case voltage seen, the minimum input voltage swing varies as
illustrated in the following table:
Input Voltage Range
Minimum Voltage Swing
0 to 2.4V
100mV
0 to VCC +0.3
200mV
R2
1.5k
R2
1.5k
R1
1.05k
R1
1.05k
GND
REFCLK
VCC
/REFCLK
Figure 3. Simplified Input Structure
Output Logic Characteristics
See
“Output Termination Recommendations” for
illustrations. In cases where single-ended output is desired,
the designer should terminate the unused complimentary
output in the same manner as the normal output that is being
used. Unused LVPECL output pairs can be left floating.
Unused LVDS output pairs should be terminated
w/100
across the pair.
LVPECL operation:
Typical voltage swing is 700mV
PP to 800mVPP into
50
.
Common mode voltage is V
CC–1.3V, typical.
100
termination across the output pair is NOT
recommended for LVPECL. See
“Output Termination”
section, Figures 3 to 5.
LVDS operation (SY89535L, Bank B)
Typical voltage swing is 250mV
PP to 450mVPP into
effective 50
.
Common mode voltage is 1.25V, typical.
100
termination across differential output pair is
fine.
Thermal Considerations
This part has an exposed die pad for enhanced heat
dissipation. We strongly recommend soldering the exposed
die pad to a ground plane. Where this is not possible, we
recommend maintaining at least 500lfpm air flow around the
part.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89534LHZ TR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Precision Programmable Bus Clock Synthesizer (Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89534LHZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER |
| SY89535L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89535LHC | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89535LHCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER |
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