參數(shù)資料
型號: SY89529L
英文描述: High Voltage Rectifer Diodes
中文描述: 3.3精密200MHz的擴頻時鐘合成器
文件頁數(shù): 3/10頁
文件大小: 314K
代理商: SY89529L
3
ClockWorks
SY89529L
Micrel
Input/Output Pins
Pin Number
SOIC
Pin Number
TQFP
Pin Name
I/O
Pin Function
25,26
8, 9
XTAL1, XTAL2
Analog
Inputs
These pins form an oscillator when connected to an external
crystal. Either series or parallel-resonant crystals are
acceptable. Connect directly to the device.
10, 11
23, 24
SSC Control (0:1)
LVTTL
Inputs
LVTTL-compatible spread-spectrum control pins. Data on
control pins maintain device control. For spread-spectrum
operation, leave SSC_0 and SSC_1 pins floating (default is
spread ON). To reconfigure the device, simply change the
SSC and the device will respond dynamically.
SSC_0 = 24k
pullup. SSC_1 = 24k
pulldown
16, 17
30, 31
FOUT, /FOUT
Differential
Differential, LVPECL clock outputs. These outputs must be
terminated to V
CC
2V. (see Figure 6)
Used for the R//C PLL loop filter. (see Figure 2.)
23
6
LOOP_FILTER
Analog I/O
24
7
LOOP_REF
Analog I/O
Provides the reference voltage for the PLL. (see Figure 2).
13
27
TEST INPUT
LVTTL
Inputs
Pin is used for test and debug purposes. Is intended to be
left floating in production environment. Programmed as
input in PLL-bypass mode. Pin includes an internal 24k
pullup resistor.
Power Supply Pins
Pin Number
SOIC
Pin Number
TQFP
Pin Name
I/O
Pin Function
14, 27
10, 28
V
CC1
, V
CC_TTL
Logic
Power
3.3V LVTTL core logic power-supply pins. Connect each
pin directly to the logic-supply plane and use proper
bypassing at each pin as close to the pin as possible; Ferrite
bead in parallel with 1
μ
F//0.01
μ
F capacitors. (see Figure 5
for typical bypass circuit.)
22
5
ANALOG_ V
CC
Power
PLL
3.3V PLL core supply pin. Must be a noise free supply.
Bypass as close to the pin as possible; ferrite bead in
parallel with 1
μ
F//0.01
μ
F capacitors.
(
see Figure 5 for
typical bypass circuit.)
18
32
V
CC_OUT
Output
Power
This is the positive power supply reference for the LVPECL
outputs (FOUT and /FOUT). See Figure 5 for typical bypass
circuit.
12
26
GND_TTL
Logic
This is the ground pin for for the TTL control logic. Normally
connected to the logic ground.
21
4
GND_ANALOG
Analog
GND
This is the ground pin for the PLL Core. Normally connected
to a quiet, noise-free ground plane for low jitter perfomance.
15
29
GND_OUTPUT
Output
GND
Ground for differential outputs. Normally connected to the
logic ground plane.
No Connect Pins
Pin Number
SOIC
Pin Number
TQFP
Pin Name
I/O
Pin Function
1, 2, 3, 4, 5
6, 7, 8, 9, 19
20, 28
1, 2, 3, 11, 12, 13
14, 15, 16, 17, 18
19, 20, 21, 22, 25
NC
No
Pins are high-impedance, low leakage and are not used by
internal circuits of the device. These pins are intended to be
left floating in production.
Connect
PIN DESCRIPTIONS
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