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參數(shù)資料
| 型號(hào)： | SY89475U |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | Precision LVPECL 2:1 Multiplexer with 1:2 Fanout and Internal Termination |
| 中文描述： | 精密的LVPECL 2:1多路復(fù)用器與1:2扇出和內(nèi)部終端 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 565K |
| 代理商： | SY89475U |
Micrel, Inc.
SY89473U
Pin Description
May 2005
3
M9999-052405
hbwhelp@micrel.com
or (408) 955-1690
Pin Number
Pin Name
Pin Function
5, 2,
23, 20
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the device.
They accept AC or DC-coupled signals as small as 100mV (200mV
PP
). Note that
these inputs will default to an indeterminate state if left open. Each pin of a pair
internally terminates to a VT
pin through 50
. Please refer to the “Input Interface
Applications” section for more details.
3, 21
VREF-AC0
,
VREF-AC1
Reference Voltage: These outputs bias to V
CC
-1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin.
Bypass with 0.01μF low ESR capacitor to VCC. Maximum sink/source current is
±1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to
drive its respective VT pin. Please refer to the “Input Interface Applications” section
for more details.
4, 22
VT0
,
VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to
a VT
pin. The VT0 and VT1 pins provide a center-tap to a termination network for
maximum interface flexibility. Please refer to the “Input Interface Applications”
section for more details.
1, 6, 9, 10, 13,
19, 24
VCC
Positive Power Supply: Connect to +2.5V or +3.3V power supply. Bypass with
0.1μF//0.01μF low ESR capacitors as close to VCC pins as possible.
7, 8
11, 12
Q0, /Q0
Q1, /Q1
Differential Outputs: These differential LVPECL output pairs are a logic function of
the IN0, IN1, and SEL inputs. Please refer to the truth table below for details.
Unused output pairs can be left floating with no impact on jitter.
15
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k
pull-up resistor
and will default to a logic HIGH state if left open. V
TH
= V
CC
/2. Please refer to the
“Timing Diagram” section for more details.
14, 17, 18
GND, Exposed
Pad
Ground: Ground pins and exposed pad must be connected to the same ground
plane.
Truth Table
INPUTS
IN1
OUTPUTS
Q
IN0
/IN0
/IN1
SEL
/Q
0
1
X
X
0
0
1
1
0
X
X
0
1
0
X
X
0
1
1
0
1
X
X
1
0
1
1
0
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