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參數(shù)資料
| 型號(hào)： | SY89296UTI TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 3.2ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 3.2ns ~ 14.8ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | SY89296UTITR SY89296UTITR-ND |
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Micrel, Inc.
SY89296U
November 2011
3
M9999-112211
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
D[9:0]
CMOS, ECL, or TTL Control Bits: These control signals adjust the delay from IN to Q. See
“AC Electrical Characteristics” for delay values. In addition, see “Interface Applications”
section which illustrates the proper interfacing techniques for different logic standards.
D[9:0] contains pull-downs and defaults LOW when left floating. D0 (LSB), and D9 (MSB).
See “Typical Operating Characteristics” for delay information.
3
D10
CMOS, ECL, or TTL Control Bit: This bit is used to cascade devices for an extended
delay range. In addition, it drives CASCADE and /CASCADE. Further, D[10] contains a
pull-down and defaults LOW when left floating.
4, 5
IN, /IN
LVPECL/ECL Signal Input: Input signal to be delayed. IN contains a 75k pull-down and
will default to a logic LOW if left floating.
6
VBB
(1)
Reference Voltage Output: When using a single-ended input signal source to IN or /IN,
connect the unused input of the differential pair to this pin. This pin can also be used to
rebias AC-coupled inputs to IN and /IN. When used, de-couple to VCC using a 0.01F
capacitor, otherwise leave floating if not used. Maximum sink/source is ±0.5mA.
7
VEF
Reference Voltage Output: Connect this pin to VCF when D[9:0], and D[10] is ECL.
Logic Standard
VCF Connects to:
LVPECL
VEF(1)
CMOS
No Connect
TTL
1.5V Source
8
VCF
Reference Voltage Input: The voltage driven on VCF sets the logic transition threshold for
D[9:0], and D[10].
9, 24, 28
GND,
Exposed Pad
(2)
Negative Supply: For MLF package, exposed pad must be connected to a ground plane
that is the same potential as the ground pin.
10
LEN
ECL Control Input: When HIGH latches the D[9:0] and D[10] bits. When LOW, the D[9:0]
and D[10] latches are transparent.
11
SETMIN
ECL Control Input: When HIGH, D[9:0] registers are reset. When LOW, the delay is set by
SETMAX or D[9:0] and D[10]. SETMIN contains a pull-down and defaults LOW when left
floating.
12
SETMAX
ECL Control Input: When SETMAX is set HIGH and SETMIN is set LOW, D[9:0] =
1111111111. When SETMAX is LOW, the delay is set by SETMIN or D[9:0] and D[10].
SETMAX contains a pull-down and defaults LOW when left floating.
13, 18, 19, 22
VCC
Positive Power Supply: Bypass with 0.1F and 0.01F low ESR capacitors.
14, 15
/Cascade,
Cascade
LVPECL Differential Output: The outputs are used when cascading two or more
SY89296U to extend the delay range.
16
/EN
LVPECL Single-Ended Control Input: When LOW, Q is delayed from IN. When HIGH, Q is
a differential LOW. /EN contains a pull-down and defaults LOW when left floating.
20, 21
/Q, Q
LVPECL Differential Output: Q is a delayed version of IN, Always terminates the output
with 50 to VCC – 2V. See “Output Interface Applications” section.
17
FTUNE
Voltage Control Input: By varying the voltage, the delay is fine tuned, see the graph,
“Propagation Delay vs. FTUNE Voltage.” Leave pin floating if not used.
Notes
:
1.
Single-ended operation is only functional at 3.3V.
2.
MLF package only.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89297U | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:2.5/3.3V, 3.2Gbps Precision CML |
| SY89297UMG | 功能描述:延遲線(xiàn)/計(jì)時(shí)元素 2.5/3.3V Dual Channel Delay Line with 5ps Step Delay (improved SY89295), Industrial, Recommended for New Designs RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89297UMG TR | 功能描述:延遲線(xiàn)/計(jì)時(shí)元素 2.5/3.3V Dual Channel Delay Line with 5ps Step Delay (improved SY89295), Industrial, Recommended for New Designs RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89297UMGTR | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:2.5/3.3V, 3.2Gbps Precision CML |
| SY89297UMH | 功能描述:延遲線(xiàn)/計(jì)時(shí)元素 2.5V Dual Channel Delay Line with 5ps Step Delay (improved SY89295) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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